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kestrel: Update the l2 cache size to fully utilize bram (88% used instead of 22%) - no reason to waste the space.

Before this change, the BRAM was allocated as follows: 128 bit cache width / 8 bit granularity = 16 ram blocks 8192/16 = 512 bytes per ram block.

With this change, the size is 2Kb per BRAM cell, which results in an 88% utilization according to the yosys report:

  Selecting best of 6 rules:
    Efficiency for rule 4.5: efficiency=12, cells=8, acells=1
    Efficiency for rule 4.4: efficiency=25, cells=4, acells=1
    Efficiency for rule 4.3: efficiency=50, cells=2, acells=1
    Efficiency for rule 4.2: efficiency=88, cells=1, acells=1
    Efficiency for rule 4.1: efficiency=44, cells=2, acells=2
    Efficiency for rule 1.1: efficiency=22, cells=4, acells=4
    Selected rule 4.2 with efficiency 88.
    Mapping to bram type $__ECP5_DP16KD (variant 2):
      Shuffle bit order to accommodate enable buckets of size 9..
      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
      Write port #0 is in clock domain \aquila_lpc_slave_wishbone.lpc_slave_interface.ipmi_bt_input_xfer_write_clk.
        Mapped to bram port A1.
      Read port #0 is in clock domain \aquila_lpc_slave_wishbone.lpc_slave_interface.ipmi_bt_input_xfer_write_clk.
        Mapped to bram port B1.1.
      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: data_mem_grain0.0.0.0

Compared to:

  Selecting best of 5 rules:
    Efficiency for rule 4.4: efficiency=6, cells=4, acells=1
    Efficiency for rule 4.3: efficiency=12, cells=2, acells=1
    Efficiency for rule 4.2: efficiency=22, cells=1, acells=1
    Efficiency for rule 4.1: efficiency=22, cells=1, acells=1
    Efficiency for rule 1.1: efficiency=22, cells=1, acells=1
    Selected rule 4.2 with efficiency 22.
    Mapping to bram type $__ECP5_DP16KD (variant 2):
      Shuffle bit order to accommodate enable buckets of size 9..
      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
      Write port #0 is in clock domain \aquila_lpc_slave_wishbone.lpc_slave_interface.ipmi_bt_input_xfer_write_clk.
        Mapped to bram port A1.
      Read port #0 is in clock domain \aquila_lpc_slave_wishbone.lpc_slave_interface.ipmi_bt_input_xfer_write_clk.
        Mapped to bram port B1.1.
      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: data_mem_grain0.0.0.0