litex_boards/targets/versa_ecp5.py · a9ed41b6068236de7ce5b5ad0e80353be22817ca · Kestrel Collaboration / Kestrel LiteX / litex-boards · GitLab

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Add ability to deassert CS after a configured idle interval · a9ed41b6

Raptor Engineering Development Team authored Jun 27, 2020

Do not attempt merged Flashed read/writes during 32-bit CPU accesses in non-merged mode
Split Kestrel SPI defines into dedicated header

a9ed41b6

versa_ecp5.py 18.8 KB

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