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Kestrel Collaboration
Kestrel LiteX
litex-boards
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2b17dc1b89894facc34495f783d670df351fd090
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litex-boards
litex_boards
targets
aller.py
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target: add rst signal to CRG to allow full reset of the SoC on reboot command.
· 2b17dc1b
Florent Kermarrec
authored
Nov 04, 2020
2b17dc1b
aller.py
6.47 KB
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