litex_boards/targets/kcu105.py · 21207533b0ca6abd21e747dfd8b4c518318931a7 · Kestrel Collaboration / Kestrel LiteX / litex-boards · GitLab

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targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to... · 21207533
Florent Kermarrec authored Mar 04, 2021
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targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).
```
21207533

kcu105.py 8.62 KB

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