litex_boards/targets/versa_ecp5.py · 1356ebb416502d42620eeb66723508dee2b20aa3 · Kestrel Collaboration / Kestrel LiteX / litex-boards · GitLab

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targets/ecp5: update clocking on boards with DDR3 to use reset from... · 1356ebb4
Florent Kermarrec authored Jun 29, 2020
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targets/ecp5: update clocking on boards with DDR3 to use reset from ddrphy.init and use primary clock for Power on reset.
```
1356ebb4

versa_ecp5.py 6.47 KB

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