c10lprefkit.py 4.9 KB
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#!/usr/bin/env python3

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#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019 Antti Lukats <antti.lukats@gmail.com>
# Copyright (c) 2019 msloniewski <marcin.sloniewski@gmail.com>
# Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse

from migen import *

from litex_boards.platforms import c10lprefkit

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from litex.soc.cores.clock import Cyclone10LPPLL
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from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT48LC16M16
from litedram.phy import GENSDRPHY

from liteeth.phy.mii import LiteEthPHYMII

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from litehyperbus.core.hyperbus import HyperRAM
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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    def __init__(self, platform, sys_clk_freq):
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        self.rst = Signal()
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        self.clock_domains.cd_sys    = ClockDomain()
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        self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
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        # # #

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        # Clk / Rst
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        clk12 = platform.request("clk12")
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        # PLL
        self.submodules.pll = pll = Cyclone10LPPLL(speedgrade="-A7")
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        self.comb += pll.reset.eq(~platform.request("cpu_reset") | self.rst)
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        pll.register_clkin(clk12, 12e6)
        pll.create_clkout(self.cd_sys,    sys_clk_freq)
        pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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        # SDRAM clock
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        self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)

# BaseSoC ------------------------------------------------------------------------------------------

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class BaseSoC(SoCCore):
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    mem_map = {
        "hyperram": 0x20000000,
    }
    mem_map.update(SoCCore.mem_map)

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    def __init__(self, sys_clk_freq=int(50e6), with_ethernet=False, **kwargs):
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        platform = c10lprefkit.Platform()
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        # SoCCore ----------------------------------------------------------------------------------
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        SoCCore.__init__(self, platform, sys_clk_freq,
            ident          = "LiteX SoC on C10 LP RefKit",
            ident_version  = True,
            **kwargs)
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        # CRG --------------------------------------------------------------------------------------
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        self.submodules.crg = _CRG(platform, sys_clk_freq)
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        # HyperRam ---------------------------------------------------------------------------------
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        self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
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        self.add_wb_slave(self.mem_map["hyperram"], self.hyperram.bus)
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        self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)

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        # SDR SDRAM --------------------------------------------------------------------------------
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        if not self.integrated_main_ram_size:
            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
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            self.add_sdram("sdram",
                phy                     = self.sdrphy,
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                module                  = MT48LC16M16(sys_clk_freq, "1:1"),
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                origin                  = self.mem_map["main_ram"],
                size                    = kwargs.get("max_sdram_size", 0x40000000),
                l2_cache_size           = kwargs.get("l2_size", 8192),
                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
                l2_cache_reverse        = True
            )
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        # Ethernet ---------------------------------------------------------------------------------
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        if with_ethernet:
            self.submodules.ethphy = LiteEthPHYMII(
                clock_pads = self.platform.request("eth_clocks"),
                pads       = self.platform.request("eth"))
            self.add_csr("ethphy")
            self.add_ethernet(phy=self.ethphy)
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        # Leds -------------------------------------------------------------------------------------
        self.submodules.leds = LedChaser(
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            pads         = platform.request_all("user_led"),
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            sys_clk_freq = sys_clk_freq)
        self.add_csr("leds")

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# Build --------------------------------------------------------------------------------------------

def main():
    parser = argparse.ArgumentParser(description="LiteX SoC on C10 LP RefKit")
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    parser.add_argument("--build", action="store_true", help="Build bitstream")
    parser.add_argument("--load",  action="store_true", help="Load bitstream")
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    builder_args(parser)
    soc_sdram_args(parser)
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    parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
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    args = parser.parse_args()

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    soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
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    builder = Builder(soc, **builder_argdict(args))
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    builder.build(run=args.build)
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    if args.load:
        prog = soc.platform.create_programmer()
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        prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
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if __name__ == "__main__":
    main()