1. 19 Mar, 2021 1 commit
  2. 12 Mar, 2021 1 commit
    • Marek Czerski's avatar
      allow for different nrxslots and ntxslots · 017b457b
      Marek Czerski authored
      Background:
      When there is a lot of broadcasts in the network, receive buffers
      may overflow easly. Especially having onlu 2 of them.
      To prevent that you can enlarge nrxslots, but because
      nrxslots + ntxslots must be the power of two, you must also
      inrease ntxslots. But there is no need to have more than 2 tx
      buffers (they work as ping-pong buffer), the CPU will not use
      more than two buffers.
      
      So being able to set for example nrxslots=8 and ntxslots=2
      is quite reasonable.
      017b457b
  3. 11 Mar, 2021 1 commit
  4. 16 Feb, 2021 2 commits
  5. 10 Feb, 2021 3 commits
  6. 27 Jan, 2021 1 commit
  7. 28 Dec, 2020 1 commit
    • Florent Kermarrec's avatar
      liteth/phy/rmii: add support for ref_clk as input. · 74481703
      Florent Kermarrec authored
      In some hardware, ref_clk can be input for both the MAC and the PHY. In this
      case, setting refclk_cd to None will make the CRG use ref_clk as the RMII
      input reference clock:
      
      Pads:
      # RMII Ethernet
      ("eth_clocks", 0,
          Subsignal("ref_clk", Pins("D17")),
          IOStandard("LVCMOS33"),
      ),
      ("eth", 0,
          Subsignal("rst_n",   Pins("F16")),
          Subsignal("rx_data", Pins("A20 B18")),
          Subsignal("crs_dv",  Pins("C20")),
          Subsignal("tx_en",   Pins("A19")),
          Subsignal("tx_data", Pins("C18 C19")),
          Subsignal("mdc",     Pins("F14")),
          Subsignal("mdio",    Pins("F13")),
          Subsignal("rx_er",   Pins("B20")),
          Subsignal("int_n",   Pins("D21")),
          IOStandard("LVCMOS33")
      ),
      
      
      PHY:
      
      self.submodules.ethphy = LiteEthPHYRMII(
          clock_pads = self.platform.request("eth_clocks"),
          pads       = self.platform.request("eth"),
          refclk_cd  = None)
      
      Thanks @mwick83 for reporting the use case and for the initial implementation.
      74481703
  8. 23 Dec, 2020 1 commit
  9. 17 Dec, 2020 2 commits
  10. 26 Nov, 2020 3 commits
  11. 25 Nov, 2020 4 commits
  12. 24 Nov, 2020 5 commits
  13. 23 Nov, 2020 9 commits
  14. 07 Nov, 2020 1 commit
  15. 06 Nov, 2020 2 commits
  16. 12 Oct, 2020 3 commits