- 19 Mar, 2021 1 commit
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enjoy-digital authored
allow for different nrxslots and ntxslots
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- 12 Mar, 2021 1 commit
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Marek Czerski authored
Background: When there is a lot of broadcasts in the network, receive buffers may overflow easly. Especially having onlu 2 of them. To prevent that you can enlarge nrxslots, but because nrxslots + ntxslots must be the power of two, you must also inrease ntxslots. But there is no need to have more than 2 tx buffers (they work as ping-pong buffer), the CPU will not use more than two buffers. So being able to set for example nrxslots=8 and ntxslots=2 is quite reasonable.
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- 11 Mar, 2021 1 commit
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Florent Kermarrec authored
mac: Use FullMemoryWE on LiteEthMACWishboneInterface to allow correct block ram inteference on Intel/Altera decices.
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- 16 Feb, 2021 2 commits
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enjoy-digital authored
Fix "is not" literal SyntaxWarning
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Joel Stanley authored
Signed-off-by: Joel Stanley <joel@jms.id.au>
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- 10 Feb, 2021 3 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 27 Jan, 2021 1 commit
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Florent Kermarrec authored
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- 28 Dec, 2020 1 commit
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Florent Kermarrec authored
In some hardware, ref_clk can be input for both the MAC and the PHY. In this case, setting refclk_cd to None will make the CRG use ref_clk as the RMII input reference clock: Pads: # RMII Ethernet ("eth_clocks", 0, Subsignal("ref_clk", Pins("D17")), IOStandard("LVCMOS33"), ), ("eth", 0, Subsignal("rst_n", Pins("F16")), Subsignal("rx_data", Pins("A20 B18")), Subsignal("crs_dv", Pins("C20")), Subsignal("tx_en", Pins("A19")), Subsignal("tx_data", Pins("C18 C19")), Subsignal("mdc", Pins("F14")), Subsignal("mdio", Pins("F13")), Subsignal("rx_er", Pins("B20")), Subsignal("int_n", Pins("D21")), IOStandard("LVCMOS33") ), PHY: self.submodules.ethphy = LiteEthPHYRMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth"), refclk_cd = None) Thanks @mwick83 for reporting the use case and for the initial implementation.
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- 23 Dec, 2020 1 commit
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Florent Kermarrec authored
phy/rmii: add refclk_cd parameter (to select reference eth clock domain) and make clock_pads optional.
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- 17 Dec, 2020 2 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 26 Nov, 2020 3 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
This ensures the full Etherbone packet is available before starting the transmission and fixes transmission issues with larges bursts or slow sys_clk_freq.
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Florent Kermarrec authored
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- 25 Nov, 2020 4 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
Useful to compare performance with RemoteClient and CommUDP.
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 24 Nov, 2020 5 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
software/dissector: merge bit.lua/etherbone.lua in a single script and enable dissector on UDP port 1234 (LiteX's default).
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 23 Nov, 2020 9 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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enjoy-digital authored
Fix syntax and load error in Wireshark etherbone dissector
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 07 Nov, 2020 1 commit
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rprinz08 authored
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- 06 Nov, 2020 2 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 12 Oct, 2020 3 commits
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enjoy-digital authored
phy/ecp5rgmii: Fix io delay blocks
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enjoy-digital authored
test_etherbone: Fix import of etherbone module
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enjoy-digital authored
mac/core: Improve timing closure of core
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