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Kestrel Collaboration
Kestrel LiteX
litedram
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9a50f6ece66a837a0879fba6dd346c7cf68196f8
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litedram
bench
ddr4_mr_gen.py
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bench/ddr4_mr_gen.py: change default cl to 9 (cl value for sys_clk_freq=125e6).
· 9a50f6ec
Florent Kermarrec
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Nov 06, 2020
9a50f6ec
ddr4_mr_gen.py
4.18 KB
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