Commit 087b7f0d authored by Luke Kenneth Casson Leighton's avatar Luke Kenneth Casson Leighton
Browse files

update pinmux submodule, rename to "fabric"

parent 557e6d75
pinmux @ 7cbf0e2a
Subproject commit d96f737c0a53dde983060522816bbef016b449ce
Subproject commit 7cbf0e2a54448f549243cd602ebafd10de8d32f0
......@@ -98,7 +98,7 @@ def load_pinouts(chipname=None):
# path is relative to this filename, in the pinmux submodule
pinmux = os.getenv("PINMUX", "%s/../../../pinmux" % pth)
fname = "%s/%s/litex_pinpads.json" % (pinmux, chipname)
fname = "%s/%s/fabric_pinpads.json" % (pinmux, chipname)
with open(fname) as f:
txt = f.read()
......
ls180_pins.py
......@@ -209,7 +209,7 @@ class TestIssuerBase(Elaboratable):
#self.dbg_domain = "sync" # sigh "dbgsunc" too problematic
self.dbg_domain = "dbgsync" # domain for DMI/JTAG clock
if self.jtag_en:
# XXX MUST keep this up-to-date with litex, and
# XXX MUST keep this up-to-date with fabric, and
# soc-cocotb-sim, and err.. all needs sorting out, argh
subset = ['uart',
'mtwi',
......@@ -415,7 +415,7 @@ class TestIssuerBase(Elaboratable):
cur_state = self.cur_state
# 4x 4k SRAM blocks. these simply "exist", they get routed in litex
# 4x 4k SRAM blocks. these simply "exist", they get routed in fabric
if self.sram4x4k:
for i, sram in enumerate(self.sram4k):
m.submodules["sram4k_%d" % i] = csd(sram)
......@@ -435,7 +435,7 @@ class TestIssuerBase(Elaboratable):
m.submodules.simple_gpio = simple_gpio = csd(self.simple_gpio)
# connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
# XXX causes litex ECP5 test to get wrong idea about input and output
# XXX causes fabric ECP5 test to get wrong idea about input and output
# (but works with verilator sim *sigh*)
# if self.gpio and self.xics:
# comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment