- 17 Mar, 2021 1 commit
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Evan Lojewski authored
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- 16 Mar, 2021 3 commits
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Evan Lojewski authored
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Evan Lojewski authored
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Evan Lojewski authored
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- 14 Mar, 2021 4 commits
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Evan Lojewski authored
- Add common routines for cpu0/cpu1 - Wrap CPU1 code in #ifdef I3CMASTER2_BASE in teh event that the FPGA was not build with the additioanl i2c master.
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Evan Lojewski authored
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Evan Lojewski authored
- Fix description for 64MB flash chips to be 512Mb not 512MB - Add Support for the 128MB flash chips
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Evan Lojewski authored
Previously, back to back FSI transactions could happen before teh FSI state machine was complete. This ensures that the FSI master does not ahve an active transaction before starting a new one. This could result in logs such as: access_fsi_mem(): address 0x002820, data: 0x00000000 sta: 0x41000001 access_fsi_mem(): address 0x002804, data: 0x00000000 sta: 0x12000000 vs access_fsi_mem(): address 0x002820, data: 0x00000000 sta: 0x41000001 access_fsi_mem(): address 0x002804, data: 0x04c04000 sta: 0x41000001 As a result, the CPU often failed to start.
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- 13 Mar, 2021 2 commits
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Evan Lojewski authored
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Evan Lojewski authored
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- 12 Mar, 2021 1 commit
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Evan Lojewski authored
build: Enable clang-formatting various source files. See merge request !2
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- 10 Mar, 2021 1 commit
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Evan Lojewski authored
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- 09 Mar, 2021 4 commits
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Evan Lojewski authored
Switch from make/gcc based build system to CMake/clang based like the bootrom. See merge request !1
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Evan Lojewski authored
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Evan Lojewski authored
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Evan Lojewski authored
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- 07 Mar, 2021 2 commits
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Evan Lojewski authored
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Evan Lojewski authored
Source: https://gitlab.raptorengineering.com/kestrel-collaboration/kestrel-litex/litex-boards (6b4b07c14132f487654dab6c5f85c63e2720c295)
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