- 05 Mar, 2021 1 commit
-
-
Jonathan Currier authored
The PowerPC ISA allows for some amount of interrupt vector table relocation, but it is defined in the context of a hypervisor. Kestrel/microwatt does not implement hypervisor, and so lacks the associated registers and logic. Introduce a simple register to set the interrupt vector table base. Kestrel arch interrupt vector base: KAIVB. Provides mapping of 48 bits (bits 14:61) of a 16KiB aligned table.
-
- 15 Jan, 2021 1 commit
-
-
Raptor Engineering Development Team authored
-
- 22 Jul, 2020 1 commit
-
-
Raptor Engineering Development Team authored
-
- 30 Jun, 2020 4 commits
-
-
LiteX authored
-
LiteX authored
Updated data to v0.0-695-gce0205b2 based on ce0205b2 from https://github.com/antonblanchard/microwatt. > commit ce0205b2 > Merge: 419c9a68 74062195 > Author: Michael Neuling <mikey@neuling.org> > Date: Tue Jun 30 15:47:36 2020 +1000 > > Merge pull request #216 from paulusmack/cfar > > Timing and speed improvements, implement CFAR register > Updated using 0.0.post60 from https://github.com/litex-hub/litex-data-auto
-
Michael Neuling authored
Timing and speed improvements, implement CFAR register
-
Paul Mackerras authored
Icache constants cleanup
-
- 29 Jun, 2020 9 commits
-
-
Paul Mackerras authored
This adds a path to allow the CR result of one instruction to be forwarded to the next instruction, so that sequences such as cmp; bc can avoid having a 1-cycle bubble. Forwarding is not available for dot-form (Rc=1) instructions, since the CR result for them is calculated in writeback. The decode.output_cr field is used to identify those instructions that compute the CR result in execute1. For some reason, the multiply instructions incorrectly had output_cr = 1 in the decode tables. This fixes that. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
-
Paul Mackerras authored
This latches the redirect signal inside execute1, so that it is sent a cycle later to fetch1 (and to decode/icache as flush). This breaks a long combinatorial chain from the branch and interrupt detection in execute1 through the redirect/flush signals all the way back to fetch1, icache and decode. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
-
Paul Mackerras authored
It's not needed for the other ops (popcnt, parity, etc.) and the logical unit shows up as a critical path from time to time. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
-
Paul Mackerras authored
This implements the CFAR SPR as a slow SPR stored in 'ctrl'. Taken branches and rfid update it to the address of the branch or rfid instruction. To simplify the logic, this makes rfid use the branch logic to generate its redirect (requiring SRR0 to come in to execute1 on the B input and SRR1 on the A input), and the masking of the bottom 2 bits of NIA is moved to fetch1. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
-
LiteX authored
-
LiteX authored
Updated data to v0.0-688-g57604c1a based on 57604c1a from https://github.com/antonblanchard/microwatt. > commit 57604c1a > Merge: 9bbef035 434962bc > Author: Michael Neuling <mikey@neuling.org> > Date: Mon Jun 29 12:19:06 2020 +1000 > > Merge pull request #213 from ozbenh/uart16550 > > Add support for standard 16550 style UART > Updated using 0.0.post60 from https://github.com/litex-hub/litex-data-auto
-
Michael Neuling authored
Add support for standard 16550 style UART
-
Michael Neuling authored
liteeth: Hook up LiteX LiteEth ethernet controller
-
Michael Neuling authored
Fix ld error in elf maketarget
-
- 26 Jun, 2020 1 commit
-
-
Boris Shingarov authored
The sdram_init ELF fails to link: powerpc64le-linux-gnu-ld -static -nostdlib -T sdram_init.lds \ --gc-sections -o sdram_init.elf head.o main.o sdram.o console.o \ libc.o sdram_init.lds powerpc64le-linux-gnu-ld: error: linker script file 'sdram_init.lds' appears multiple times make: *** [Makefile:70: sdram_init.elf] Error 1 This is because sdram_init.lds is one of the prerequisites, and thus is contained in $^. However, it is also explicitly specified as part of LDFLAGS, as the argument to -T. Signed-off-by: Boris Shingarov <shingarov@labware.com>
-
- 25 Jun, 2020 3 commits
-
-
Benjamin Herrenschmidt authored
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-
Benjamin Herrenschmidt authored
Under some circumstances we get POLLHUP which we incorrectly treat as having a character in the buffer. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-
Benjamin Herrenschmidt authored
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-
- 24 Jun, 2020 2 commits
-
-
LiteX authored
-
LiteX authored
Updated data to v0.0-673-g7566f04f based on 7566f04f from https://github.com/antonblanchard/microwatt. > commit 7566f04f > Merge: 695e081c 60e5f7b9 > Author: Michael Neuling <mikey@neuling.org> > Date: Tue Jun 23 16:58:06 2020 +1000 > > Merge pull request #211 from shenki/spi-constraint > > spi: Fix dat_i_l constraints > Updated using 0.0.post60 from https://github.com/litex-hub/litex-data-auto
-
- 23 Jun, 2020 13 commits
-
-
Benjamin Herrenschmidt authored
This adds a flag (currently not set) to indicate that the core is using the architected timebase frequency of 512Mhz. When not set, the core is using the proc frequency for the timebase. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-
Benjamin Herrenschmidt authored
And rebuild various binaries Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-
Benjamin Herrenschmidt authored
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-
Benjamin Herrenschmidt authored
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-
Benjamin Herrenschmidt authored
Use a more generic console_init() instead of potato_uart_init(), and do the same for interrupt control. There should be no change in behaviour. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-
Benjamin Herrenschmidt authored
This imports via fusesoc a 16550 compatible (ie "standard") UART, and wires it up optionally in the SoC instead of the potato one. This also adds support for a second UART (which is always a 16550) to Arty, wired to JC "bottom" port. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-
Benjamin Herrenschmidt authored
It's used by the boot wrapper in Linux and possibly some userspace programs. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-
Benjamin Herrenschmidt authored
Currently only generated for Arty. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-
Michael Neuling authored
spi: Fix dat_i_l constraints
-
LiteX authored
-
LiteX authored
Updated data to v0.0-671-g695e081c based on 695e081c from https://github.com/antonblanchard/microwatt. > commit 695e081c > Merge: b90a0a21 bb54af59 > Author: Michael Neuling <mikey@neuling.org> > Date: Tue Jun 23 14:32:42 2020 +1000 > > Merge pull request #210 from ozbenh/xics > > xics: Cleanups and add a simple ICS for use by Linux > Updated using 0.0.post60 from https://github.com/litex-hub/litex-data-auto
-
Joel Stanley authored
No cells matched 'get_cells -hierarchical -filter {NAME =~*/spi_rxtx/dat_i_l*}'. [build/microwatt_0/src/microwatt_0/fpga/arty_a7.xdc:42] The signal is in it's own process so the net name ends up being spi_rxtx/input_delay_1.dat_i_l_reg. After this change the log shows: Applied set_property IOB = TRUE for soc0/\spiflash_gen.spiflash /spi_rxtx/\input_delay_1.dat_i_l_reg . (constraint file fpga/arty_a7.xdc, line 42). Applied set_property IOB = TRUE for soc0/\spiflash_gen.spiflash /spi_rxtx/\input_delay_1.dat_i_l_reg . (constraint file fpga/arty_a7.xdc, line 42). Applied set_property IOB = TRUE for soc0/\spiflash_gen.spiflash /spi_rxtx/\input_delay_1.dat_i_l_reg . (constraint file fpga/arty_a7.xdc, line 42). Applied set_property IOB = TRUE for soc0/\spiflash_gen.spiflash /spi_rxtx/\input_delay_1.dat_i_l_reg . (constraint file fpga/arty_a7.xdc, line 42). Signed-off-by: Joel Stanley <joel@jms.id.au>
-
Michael Neuling authored
xics: Cleanups and add a simple ICS for use by Linux
-
- 22 Jun, 2020 1 commit
-
-
Benjamin Herrenschmidt authored
This makes the ICS support less than the 8 architected bits and sets the soc to use 3 bits by default. All the supported bits set translates to "masked" (and will read back at 0xff), any small value is used as-is. Linux doesn't use priorities above 5, so this is a way to save silicon. The number of supported priority bits is exposed to the OS via the config register. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-
- 19 Jun, 2020 4 commits
-
-
Benjamin Herrenschmidt authored
Move the external interrupt generation to a separate module "ICS" (source controller) which a register per source containing currently only the priority control. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-
Benjamin Herrenschmidt authored
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-
Benjamin Herrenschmidt authored
In case it would be tempted to "read ahead" the delay function Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-
Benjamin Herrenschmidt authored
That's how Linux expects it. This also simplifies the register access implementation since the bit fields now align properly regardless of the access size. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-