Disable DMI logfile to save some die area on smaller FPGAs

pythondata_cpu_microwatt/vhdl/core.vhdl

@@ -12,7 +12,7 @@ entity core is
 	DISABLE_FLATTEN : boolean := false;
         EX1_BYPASS : boolean := true;
 	ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
-        LOG_LENGTH : natural := 512
+        LOG_LENGTH : natural := 0
         );
     port (
         clk          : in std_ulogic;