- 24 Jul, 2019 2 commits
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Raptor Engineering Development Team authored
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Xing Zhao authored
Talos lite has only one socket and unmounted all the components related to the second CPU. False power good of the second CPU's power may casue the system poweroff fail. So gate the power good of the second CPU's power by the present signal of the second CPU. Signed-off-by: Xing Zhao <zxingsh@cn.ibm.com>
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- 16 May, 2019 1 commit
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Raptor Engineering Development Team authored
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- 30 Apr, 2019 2 commits
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Raptor Engineering Development Team authored
This breaks compatibility with PCB revision 1.00
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Raptor Engineering Development Team authored
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- 29 Apr, 2019 1 commit
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Raptor Engineering Development Team authored
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- 14 Mar, 2019 1 commit
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Raptor Engineering Development Team authored
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- 14 Jun, 2018 1 commit
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Raptor Engineering Development Team authored
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- 11 Jun, 2018 1 commit
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Raptor Engineering Development Team authored
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- 06 Jun, 2018 1 commit
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Raptor Engineering Development Team authored
Bump FPGA version
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- 18 May, 2018 1 commit
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Raptor Engineering Development Team authored
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- 13 May, 2018 2 commits
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Raptor Engineering Development Team authored
ATX PG must remain high for minimum periods according to the specification Don't try to work around faulty external power supply designs
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Raptor Engineering Development Team authored
Expose mode select jumper to host Switch ATX PG filter to slower clock source and reduce counter width Bump FPGA version in preparation for release
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- 03 May, 2018 1 commit
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Raptor Engineering Development Team authored
The ATX specification allows up to 500ms for the ATX power good signal to be asserted after power on request Extend time from power on request to fault condition set to about 800ms in order to ensure that PSUs close to the specification margins do not induce spurious faults.
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- 26 Apr, 2018 1 commit
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Raptor Engineering Development Team authored
Reset now attempted after 30 seconds of failure to exit U-boot
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- 23 Apr, 2018 1 commit
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Raptor Engineering Development Team authored
Debounce ATX power good to work around certain Delta PSUs asserting PG before rails can be loaded Initialize various registers to 0 to save die area Bump version number for further development
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- 15 Apr, 2018 1 commit
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Raptor Engineering Development Team authored
Bump revision number reported to 0x07
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- 12 Apr, 2018 1 commit
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Raptor Engineering Development Team authored
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- 08 Mar, 2018 1 commit
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Raptor Engineering Development Team authored
This works around ASpeed fast blink boot hang errata (app note #3)
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- 19 Feb, 2018 1 commit
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Raptor Engineering Development Team authored
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- 13 Feb, 2018 1 commit
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Raptor Engineering Development Team authored
Explicitly call out register addresses
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- 28 Jan, 2018 1 commit
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Raptor Engineering Development Team authored
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- 23 Jan, 2018 1 commit
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Raptor Engineering Development Team authored
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- 22 Jan, 2018 2 commits
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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- 19 Jan, 2018 1 commit
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Raptor Engineering Development Team authored
Add front panel LED override
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- 18 Jan, 2018 1 commit
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Raptor Engineering Development Team authored
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- 17 Jan, 2018 6 commits
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Raptor Engineering Development Team authored
1.) Initial power-on / U-Boot: KR pattern 2.) Kernel / userspace booting: fading pattern
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Raptor Engineering Development Team authored
Use fading startup pattern instead of prior KR pattern
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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- 16 Jan, 2018 1 commit
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Raptor Engineering Development Team authored
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- 14 Jan, 2018 1 commit
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Raptor Engineering Development Team authored
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- 12 Jan, 2018 1 commit
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Raptor Engineering Development Team authored
Add initial internal oscillator Fix license in PCF file Tested to work on initial Talos™ II hardware
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- 07 Jan, 2018 1 commit
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Raptor Engineering Development Team authored
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- 31 Dec, 2017 3 commits
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Raptor Engineering Development Team authored
Add CPU1 presence detect to response field
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
Add initial Talos™ II system control logic
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