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Commit a5f47b42 authored by DreamSourceLab's avatar DreamSourceLab
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Add new products support (DSLogicU3Pro16/DSLogicU3Pro32/DSCopeU2B100/DSCopeU3P100)

parent 235a863b
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Showing with 1241 additions and 377 deletions
DSView/pv/dialogs/waitingdialog.cpp
View file @ a5f47b42
......@@ -170,8 +170,34 @@ void WaitingDialog::changeText()
{
tips->setText(tr("Waiting"));
index = 0;
GVariant* gvar;
bool comb_comp_en = false;
bool zero_fgain = false;
GVariant* gvar = _dev_inst->get_config(NULL, NULL, _key);
gvar = _dev_inst->get_config(NULL, NULL, SR_CONF_PROBE_COMB_COMP_EN);
if (gvar != NULL) {
comb_comp_en = g_variant_get_boolean(gvar);
g_variant_unref(gvar);
if (comb_comp_en) {
gvar = _dev_inst->get_config(NULL, NULL, SR_CONF_ZERO_COMB_FGAIN);
if (gvar != NULL) {
zero_fgain = g_variant_get_boolean(gvar);
g_variant_unref(gvar);
if (zero_fgain) {
boost::shared_ptr<view::DsoSignal> dsoSig;
BOOST_FOREACH(const boost::shared_ptr<view::Signal> s, _session.get_signals())
{
if ((dsoSig = dynamic_pointer_cast<view::DsoSignal>(s)))
dsoSig->set_enable(dsoSig->get_index() == 0);
}
boost::this_thread::sleep(boost::posix_time::millisec(100));
_dev_inst->set_config(NULL, NULL, SR_CONF_ZERO_COMB, g_variant_new_boolean(true));
}
}
}
}
gvar = _dev_inst->get_config(NULL, NULL, _key);
if (gvar != NULL) {
bool zero = g_variant_get_boolean(gvar);
g_variant_unref(gvar);
......
DSView/pv/sigsession.cpp
View file @ a5f47b42
......@@ -505,7 +505,7 @@ bool SigSession::get_capture_status(bool &triggered, int &progress)
{
uint64_t sample_limits = cur_samplelimits();
sr_status status;
if (sr_status_get(_dev_inst->dev_inst(), &status, true, SR_STATUS_TRIG_BEGIN, SR_STATUS_TRIG_END) == SR_OK){
if (sr_status_get(_dev_inst->dev_inst(), &status, true) == SR_OK){
triggered = status.trig_hit & 0x01;
uint64_t captured_cnt = status.trig_hit >> 2;
captured_cnt = ((uint64_t)status.captured_cnt0 +
......
DSView/pv/storesession.cpp
View file @ a5f47b42
......@@ -460,7 +460,7 @@ QString StoreSession::meta_gen(boost::shared_ptr<data::Snapshot> snapshot)
fprintf(meta, " vFactor%d = %" PRIu64 "\n", probecnt, probe->vfactor);
fprintf(meta, " vOffset%d = %d\n", probecnt, probe->hw_offset);
fprintf(meta, " vTrig%d = %d\n", probecnt, probe->trig_value);
if (sr_status_get(sdi, &status, false, 0, 0) == SR_OK) {
if (sr_status_get(sdi, &status, false) == SR_OK) {
if (probe->index == 0) {
fprintf(meta, " period%d = %" PRIu32 "\n", probecnt, status.ch0_cyc_tlen);
fprintf(meta, " pcnt%d = %" PRIu32 "\n", probecnt, status.ch0_cyc_cnt);
......
DSView/pv/toolbars/samplingbar.cpp
View file @ a5f47b42
......@@ -804,7 +804,7 @@ void SamplingBar::commit_settings()
g_variant_new_uint64(sample_rate));
if (dev_inst->dev_inst()->mode != DSO) {
const uint64_t sample_count = ((uint64_t)ceil(sample_duration / SR_SEC(1) *
sample_rate) + 1023ULL) & ~1023ULL;
sample_rate) + SAMPLES_ALIGN) & ~SAMPLES_ALIGN;
if (sample_count != dev_inst->get_sample_limit())
dev_inst->set_config(NULL, NULL,
SR_CONF_LIMIT_SAMPLES,
......
DSView/pv/view/dsosignal.cpp
View file @ a5f47b42
......@@ -892,7 +892,7 @@ void DsoSignal::paint_mid(QPainter &p, int left, int right, QColor fore, QColor
}
sr_status status;
if (sr_status_get(_dev_inst->dev_inst(), &status, false, 0, 0) == SR_OK) {
if (sr_status_get(_dev_inst->dev_inst(), &status, false) == SR_OK) {
_mValid = true;
if (status.measure_valid) {
_min = (index == 0) ? status.ch0_min : status.ch1_min;
......
DSView/res/DSCopeU2B100.bin 0 → 100644
View file @ a5f47b42
File added
DSView/res/DSCopeU3P100.bin 0 → 100644
View file @ a5f47b42
File added
DSView/res/DSLogic33.bin
View file @ a5f47b42
No preview for this file type
DSView/res/DSLogic50.bin
View file @ a5f47b42
No preview for this file type
DSView/res/DSLogicBasic.bin
View file @ a5f47b42
No preview for this file type
DSView/res/DSLogicPlus.bin
View file @ a5f47b42
No preview for this file type
DSView/res/DSLogicPro.bin
View file @ a5f47b42
No preview for this file type
DSView/res/DSLogicU2Basic.bin
View file @ a5f47b42
No preview for this file type
DSView/res/DSLogicU3Pro16.bin 0 → 100644
View file @ a5f47b42
File added
DSView/res/DSLogicU3Pro32.bin 0 → 100644
View file @ a5f47b42
File added
libsigrok4DSL/hardware/DSL/command.h
View file @ a5f47b42
......@@ -137,6 +137,14 @@ struct cmd_zero_info {
uint8_t trans0;
uint8_t trans1;
uint8_t comb_comp;
uint8_t fgain0_code;
uint8_t fgain1_code;
uint8_t fgain2_code;
uint8_t fgain3_code;
uint8_t comb_fgain0_code;
uint8_t comb_fgain1_code;
uint8_t comb_fgain2_code;
uint8_t comb_fgain3_code;
};
struct cmd_vga_info {
......
libsigrok4DSL/hardware/DSL/dscope.c
View file @ a5f47b42
This diff is collapsed.
libsigrok4DSL/hardware/DSL/dsl.c
View file @ a5f47b42
This diff is collapsed.
libsigrok4DSL/hardware/DSL/dsl.h
View file @ a5f47b42
......@@ -54,6 +54,7 @@
#define USB_CONFIGURATION 1
#define NUM_TRIGGER_STAGES 16
#define NUM_SIMUL_TRANSFERS 64
#define MAX_EMPTY_POLL 16
#define DSL_REQUIRED_VERSION_MAJOR 2
#define DSL_REQUIRED_VERSION_MINOR 0
......@@ -132,6 +133,11 @@
#define TRIG_CHECKID 0x55555555
#define DSO_PKTID 0xa500
/*
* zero configuration
*/
#define DSO_ZERO_PAGE 8
#define MAX_ACC_VARIANCE 0.0005
/*
* for DSCope device
* trans: x << 8 + y
......@@ -341,14 +347,14 @@ static const struct DSL_vga vga_defaults[] = {
{3, 1000, 0x57200, 45, 1024-920-45},
{3, 2000, 0x2DD00, 45, 1024-920-45},
{4, 10, 0x1C6C00, 45, 1024-945-45},
{4, 20, 0x19E000, 45, 1024-945-45},
{4, 50, 0x16A800, 45, 1024-945-45},
{4, 100, 0x142800, 45, 1024-945-45},
{4, 200, 0xC7F00, 45, 1024-945-45},
{4, 500, 0x94000, 45, 1024-945-45},
{4, 1000, 0x6CF00, 45, 1024-945-45},
{4, 2000, 0x44F00, 45, 1024-945-45},
{4, 10, 0x1C6C00, 60, 1024-900-60},
{4, 20, 0x19E000, 60, 1024-900-60},
{4, 50, 0x16A800, 60, 1024-900-60},
{4, 100, 0x142800, 60, 1024-900-60},
{4, 200, 0xC7F00, 60, 1024-900-60},
{4, 500, 0x94000, 60, 1024-900-60},
{4, 1000, 0x6CF00, 60, 1024-900-60},
{4, 2000, 0x44F00, 60, 1024-900-60},
{0, 0, 0, 0, 0}
};
......@@ -358,19 +364,36 @@ enum CHANNEL_ID {
DSL_STREAM25x12,
DSL_STREAM50x6,
DSL_STREAM100x3,
DSL_STREAM100x16,
DSL_STREAM125x16,
DSL_STREAM20x16_3DN2,
DSL_STREAM25x12_3DN2,
DSL_STREAM50x6_3DN2,
DSL_STREAM100x3_3DN2,
DSL_STREAM10x32_32_3DN2,
DSL_STREAM20x16_32_3DN2,
DSL_STREAM25x12_32_3DN2,
DSL_STREAM50x6_32_3DN2,
DSL_STREAM100x3_32_3DN2,
DSL_STREAM50x32,
DSL_STREAM100x30,
DSL_STREAM250x12,
DSL_STREAM125x16_16,
DSL_STREAM250x12_16,
DSL_STREAM500x6,
DSL_STREAM1000x3,
DSL_BUFFER100x16,
DSL_BUFFER200x8,
DSL_BUFFER400x4,
DSL_BUFFER250x32,
DSL_BUFFER500x16,
DSL_BUFFER1000x8,
DSL_ANALOG10x2,
DSL_ANALOG10x2_500,
DSL_DSO200x2,
DSL_DSO1000x2,
......@@ -403,15 +426,40 @@ static const struct DSL_channels channel_modes[] = {
SR_KHZ(10), SR_MHZ(100), 1, "Use 6 Channels (Max 50MHz)", "使用6个通道(最大采样率 50MHz)"},
{DSL_STREAM100x3, LOGIC, SR_CHANNEL_LOGIC, TRUE, 16, 3, 1, SR_KHZ(10), SR_MHZ(100),
SR_KHZ(10), SR_MHZ(100), 1, "Use 3 Channels (Max 100MHz)", "使用3个通道(最大采样率 100MHz)"},
{DSL_STREAM100x16, LOGIC, SR_CHANNEL_LOGIC, TRUE, 16, 16, 1, SR_KHZ(10), SR_MHZ(100),
SR_KHZ(10), SR_MHZ(500), 5, "Use 16 Channels (Max 100MHz)", "使用16个通道(最大采样率 100MHz)"},
{DSL_STREAM125x16, LOGIC, SR_CHANNEL_LOGIC, TRUE, 16, 16, 1, SR_KHZ(10), SR_MHZ(125),
{DSL_STREAM20x16_3DN2, LOGIC, SR_CHANNEL_LOGIC, TRUE, 16, 16, 1, SR_KHZ(10), SR_MHZ(20),
SR_KHZ(10), SR_MHZ(500), 5, "Use 16 Channels (Max 20MHz)", "使用16个通道(最大采样率 20MHz)"},
{DSL_STREAM25x12_3DN2, LOGIC, SR_CHANNEL_LOGIC, TRUE, 16, 12, 1, SR_KHZ(10), SR_MHZ(25),
SR_KHZ(10), SR_MHZ(500), 5, "Use 12 Channels (Max 25MHz)", "使用12个通道(最大采样率 25MHz)"},
{DSL_STREAM50x6_3DN2, LOGIC, SR_CHANNEL_LOGIC, TRUE, 16, 6, 1, SR_KHZ(10), SR_MHZ(50),
SR_KHZ(10), SR_MHZ(500), 5, "Use 6 Channels (Max 50MHz)", "使用6个通道(最大采样率 50MHz)"},
{DSL_STREAM100x3_3DN2, LOGIC, SR_CHANNEL_LOGIC, TRUE, 16, 3, 1, SR_KHZ(10), SR_MHZ(100),
SR_KHZ(10), SR_MHZ(500), 5, "Use 3 Channels (Max 100MHz)", "使用3个通道(最大采样率 100MHz)"},
{DSL_STREAM10x32_32_3DN2, LOGIC, SR_CHANNEL_LOGIC, TRUE, 32, 32, 1, SR_KHZ(10), SR_MHZ(10),
SR_KHZ(10), SR_MHZ(500), 5, "Use 32 Channels (Max 10MHz)", "使用32个通道(最大采样率 10MHz)"},
{DSL_STREAM20x16_32_3DN2, LOGIC, SR_CHANNEL_LOGIC, TRUE, 32, 16, 1, SR_KHZ(10), SR_MHZ(20),
SR_KHZ(10), SR_MHZ(500), 5, "Use 16 Channels (Max 20MHz)", "使用16个通道(最大采样率 20MHz)"},
{DSL_STREAM25x12_32_3DN2, LOGIC, SR_CHANNEL_LOGIC, TRUE, 32, 12, 1, SR_KHZ(10), SR_MHZ(25),
SR_KHZ(10), SR_MHZ(500), 5, "Use 12 Channels (Max 25MHz)", "使用12个通道(最大采样率 25MHz)"},
{DSL_STREAM50x6_32_3DN2, LOGIC, SR_CHANNEL_LOGIC, TRUE, 32, 6, 1, SR_KHZ(10), SR_MHZ(50),
SR_KHZ(10), SR_MHZ(500), 5, "Use 6 Channels (Max 50MHz)", "使用6个通道(最大采样率 50MHz)"},
{DSL_STREAM100x3_32_3DN2, LOGIC, SR_CHANNEL_LOGIC, TRUE, 32, 3, 1, SR_KHZ(10), SR_MHZ(100),
SR_KHZ(10), SR_MHZ(500), 5, "Use 3 Channels (Max 100MHz)", "使用3个通道(最大采样率 100MHz)"},
{DSL_STREAM50x32, LOGIC, SR_CHANNEL_LOGIC, TRUE, 32, 32, 1, SR_KHZ(10), SR_MHZ(50),
SR_KHZ(10), SR_MHZ(500), 5, "Use 32 Channels (Max 50MHz)", "使用32个通道(最大采样率 50MHz)"},
{DSL_STREAM100x30, LOGIC, SR_CHANNEL_LOGIC, TRUE, 32, 30, 1, SR_KHZ(10), SR_MHZ(100),
SR_KHZ(10), SR_MHZ(500), 5, "Use 30 Channels (Max 100MHz)", "使用30个通道(最大采样率 100MHz)"},
{DSL_STREAM250x12, LOGIC, SR_CHANNEL_LOGIC, TRUE, 32, 12, 1, SR_KHZ(10), SR_MHZ(250),
SR_KHZ(10), SR_MHZ(500), 5, "Use 12 Channels (Max 250MHz)", "使用12个通道(最大采样率 250MHz)"},
{DSL_STREAM125x16_16, LOGIC, SR_CHANNEL_LOGIC, TRUE, 16, 16, 1, SR_KHZ(10), SR_MHZ(125),
SR_KHZ(10), SR_MHZ(500), 5, "Use 16 Channels (Max 125MHz)", "使用16个通道(最大采样率 125MHz)"},
{DSL_STREAM250x12, LOGIC, SR_CHANNEL_LOGIC, TRUE, 16, 12, 1, SR_KHZ(10), SR_MHZ(250),
{DSL_STREAM250x12_16, LOGIC, SR_CHANNEL_LOGIC, TRUE, 16, 12, 1, SR_KHZ(10), SR_MHZ(250),
SR_KHZ(10), SR_MHZ(500), 5, "Use 12 Channels (Max 250MHz)", "使用12个通道(最大采样率 250MHz)"},
{DSL_STREAM500x6, LOGIC, SR_CHANNEL_LOGIC, TRUE, 16, 6, 1, SR_KHZ(10), SR_MHZ(500),
SR_KHZ(10), SR_MHZ(500), 5, "Use 6 Channels (Max 500MHz)", "使用6个通道(最大采样率 500MHz)"},
{DSL_STREAM1000x3, LOGIC, SR_CHANNEL_LOGIC, TRUE, 16, 3, 1, SR_KHZ(10), SR_GHZ(1),
{DSL_STREAM1000x3, LOGIC, SR_CHANNEL_LOGIC, TRUE, 8, 3, 1, SR_KHZ(10), SR_GHZ(1),
SR_KHZ(10), SR_MHZ(500), 5, "Use 3 Channels (Max 1GHz)", "使用3个通道(最大采样率 1GHz)"},
// LA Buffer
......@@ -421,6 +469,9 @@ static const struct DSL_channels channel_modes[] = {
SR_KHZ(10), SR_MHZ(100), 1, "Use Channels 0~7 (Max 200MHz)", "使用通道 0~7 (最大采样率 200MHz)"},
{DSL_BUFFER400x4, LOGIC, SR_CHANNEL_LOGIC, FALSE, 4, 4, 1, SR_KHZ(10), SR_MHZ(400),
SR_KHZ(10), SR_MHZ(100), 1, "Use Channels 0~3 (Max 400MHz)", "使用通道 0~3 (最大采样率 400MHz)"},
{DSL_BUFFER250x32, LOGIC, SR_CHANNEL_LOGIC, FALSE, 32, 32, 1, SR_KHZ(10), SR_MHZ(250),
SR_KHZ(10), SR_MHZ(500), 5, "Use Channels 0~31 (Max 250MHz)", "使用通道 0~31 (最大采样率 250MHz)"},
{DSL_BUFFER500x16, LOGIC, SR_CHANNEL_LOGIC, FALSE, 16, 16, 1, SR_KHZ(10), SR_MHZ(500),
SR_KHZ(10), SR_MHZ(500), 5, "Use Channels 0~15 (Max 500MHz)", "使用通道 0~15 (最大采样率 500MHz)"},
{DSL_BUFFER1000x8, LOGIC, SR_CHANNEL_LOGIC, FALSE, 8, 8, 1, SR_KHZ(10), SR_GHZ(1),
......@@ -429,12 +480,14 @@ static const struct DSL_channels channel_modes[] = {
// DAQ
{DSL_ANALOG10x2, ANALOG, SR_CHANNEL_ANALOG, TRUE, 2, 2, 8, SR_HZ(10), SR_MHZ(10),
SR_KHZ(10), SR_MHZ(100), 1, "Use Channels 0~1 (Max 10MHz)", "使用通道 0~1 (最大采样率 10MHz)"},
{DSL_ANALOG10x2_500, ANALOG, SR_CHANNEL_ANALOG, TRUE, 2, 2, 8, SR_HZ(10), SR_MHZ(10),
SR_KHZ(10), SR_MHZ(500), 1, "Use Channels 0~1 (Max 10MHz)", "使用通道 0~1 (最大采样率 10MHz)"},
// OSC
{DSL_DSO200x2, DSO, SR_CHANNEL_DSO, FALSE, 2, 2, 8, SR_KHZ(10), SR_MHZ(200),
SR_KHZ(10), SR_MHZ(100), 1, "Use Channels 0~1 (Max 200MHz)", "使用通道 0~1 (最大采样率 200MHz)"},
{DSL_DSO1000x2, DSO, SR_CHANNEL_DSO, FALSE, 2, 2, 8, SR_KHZ(10), SR_GHZ(1),
SR_KHZ(10), SR_MHZ(100), 1, "Use Channels 0~1 (Max 1GHz)", "使用通道 0~1 (最大采样率 1GHz)"}
SR_KHZ(10), SR_MHZ(500), 1, "Use Channels 0~1 (Max 1GHz)", "使用通道 0~1 (最大采样率 1GHz)"}
};
static const struct DSL_profile supported_DSLogic[] = {
......@@ -578,6 +631,114 @@ static const struct DSL_profile supported_DSLogic[] = {
SR_MHZ(400)}
},
{0x2A0E, 0x002A, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSLogic U3Pro16", NULL,
"DSLogicU3Pro16.fw",
"DSLogicU3Pro16.bin",
"DSLogicU3Pro16.bin",
{CAPS_MODE_LOGIC,
CAPS_FEATURE_VTH | CAPS_FEATURE_BUF | CAPS_FEATURE_USB30 | CAPS_FEATURE_ADF4360,
(1 << DSL_STREAM20x16_3DN2) | (1 << DSL_STREAM25x12_3DN2) | (1 << DSL_STREAM50x6_3DN2) | (1 << DSL_STREAM100x3_3DN2) |
(1 << DSL_BUFFER500x16) | (1 << DSL_BUFFER1000x8),
16,
SR_GB(2),
0,
DSL_BUFFER500x16,
0,
samplerates1000,
0,
DSL_STREAM20x16_3DN2,
SR_MHZ(1),
SR_Mn(1),
0,
0,
0,
0,
0,
SR_MHZ(500),
SR_GHZ(1)}
},
{0x2A0E, 0x002A, LIBUSB_SPEED_SUPER, "DreamSourceLab", "DSLogic U3Pro16", NULL,
"DSLogicU3Pro16.fw",
"DSLogicU3Pro16.bin",
"DSLogicU3Pro16.bin",
{CAPS_MODE_LOGIC,
CAPS_FEATURE_VTH | CAPS_FEATURE_BUF | CAPS_FEATURE_USB30 | CAPS_FEATURE_ADF4360,
(1 << DSL_STREAM125x16_16) | (1 << DSL_STREAM250x12_16) | (1 << DSL_STREAM500x6) | (1 << DSL_STREAM1000x3) |
(1 << DSL_BUFFER500x16) | (1 << DSL_BUFFER1000x8),
16,
SR_GB(2),
0,
DSL_BUFFER500x16,
0,
samplerates1000,
0,
DSL_STREAM125x16_16,
SR_MHZ(1),
SR_Mn(1),
0,
0,
0,
0,
0,
SR_MHZ(500),
SR_GHZ(1)}
},
{0x2A0E, 0x002C, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSLogic U3Pro32", NULL,
"DSLogicU3Pro32.fw",
"DSLogicU3Pro32.bin",
"DSLogicU3Pro32.bin",
{CAPS_MODE_LOGIC,
CAPS_FEATURE_VTH | CAPS_FEATURE_BUF | CAPS_FEATURE_USB30 | CAPS_FEATURE_ADF4360 | CAPS_FEATURE_LA_CH32,
(1 << DSL_STREAM10x32_32_3DN2) | (1 << DSL_STREAM20x16_32_3DN2) | (1 << DSL_STREAM25x12_32_3DN2) | (1 << DSL_STREAM50x6_32_3DN2) | (1 << DSL_STREAM100x3_32_3DN2) |
(1 << DSL_BUFFER500x16) | (1 << DSL_BUFFER1000x8),
32,
SR_GB(2),
0,
DSL_BUFFER250x32,
0,
samplerates1000,
0,
DSL_STREAM10x32_32_3DN2,
SR_MHZ(1),
SR_Mn(1),
0,
0,
0,
0,
0,
SR_MHZ(500),
SR_GHZ(1)}
},
{0x2A0E, 0x002C, LIBUSB_SPEED_SUPER, "DreamSourceLab", "DSLogic U3Pro32", NULL,
"DSLogicU3Pro32.fw",
"DSLogicU3Pro32.bin",
"DSLogicU3Pro32.bin",
{CAPS_MODE_LOGIC,
CAPS_FEATURE_VTH | CAPS_FEATURE_BUF | CAPS_FEATURE_USB30 | CAPS_FEATURE_ADF4360 | CAPS_FEATURE_LA_CH32,
(1 << DSL_STREAM50x32) | (1 << DSL_STREAM100x30) | (1 << DSL_STREAM250x12) | (1 << DSL_STREAM500x6) | (1 << DSL_STREAM1000x3) |
(1 << DSL_BUFFER250x32) | (1 << DSL_BUFFER500x16) | (1 << DSL_BUFFER1000x8),
32,
SR_GB(2),
0,
DSL_BUFFER250x32,
0,
samplerates1000,
0,
DSL_STREAM50x32,
SR_MHZ(1),
SR_Mn(1),
0,
0,
0,
0,
0,
SR_MHZ(500),
SR_GHZ(1)}
},
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}
};
......@@ -753,7 +914,7 @@ static const struct DSL_profile supported_DSCope[] = {
"DSCopeU2B20.bin",
"DSCopeU2B20.bin",
{CAPS_MODE_ANALOG | CAPS_MODE_DSO,
CAPS_FEATURE_ZERO,
CAPS_FEATURE_ZERO | CAPS_FEATURE_AUTO_VGAIN,
(1 << DSL_ANALOG10x2) |
(1 << DSL_DSO200x2),
2,
......@@ -766,8 +927,8 @@ static const struct DSL_profile supported_DSCope[] = {
DSL_DSO200x2,
SR_MHZ(100),
SR_Kn(10),
945,
1024-945,
930,
1024-930,
10,
245,
22,
......@@ -780,7 +941,7 @@ static const struct DSL_profile supported_DSCope[] = {
"DSCopeU2P20.bin",
"DSCopeU2P20.bin",
{CAPS_MODE_ANALOG | CAPS_MODE_DSO,
CAPS_FEATURE_ZERO | CAPS_FEATURE_BUF | CAPS_FEATURE_POGOPIN,
CAPS_FEATURE_ZERO | CAPS_FEATURE_BUF | CAPS_FEATURE_POGOPIN | CAPS_FEATURE_AUTO_VGAIN,
(1 << DSL_ANALOG10x2) |
(1 << DSL_DSO200x2),
2,
......@@ -793,8 +954,8 @@ static const struct DSL_profile supported_DSCope[] = {
DSL_DSO200x2,
SR_MHZ(100),
SR_Mn(1),
945,
1024-945,
930,
1024-930,
10,
245,
22,
......@@ -802,6 +963,86 @@ static const struct DSL_profile supported_DSCope[] = {
SR_HZ(0)}
},
{0x2A0E, 0x0028, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSCope U2B100", NULL,
"DSCopeU2B100.fw",
"DSCopeU2B100.bin",
"DSCopeU2B100.bin",
{CAPS_MODE_ANALOG | CAPS_MODE_DSO,
CAPS_FEATURE_ZERO | CAPS_FEATURE_HMCAD1511 | CAPS_FEATURE_20M,
(1 << DSL_ANALOG10x2_500) |
(1 << DSL_DSO1000x2),
2,
SR_KB(256),
SR_Kn(20),
0,
vdivs10to2000,
samplerates1000,
4,
DSL_DSO1000x2,
SR_MHZ(500),
SR_Kn(10),
850,
1024-850,
10,
245,
80,
SR_HZ(0),
SR_HZ(0)}
},
{0x2A0E, 0x002B, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSCope U3P100", NULL,
"DSCopeU3P100.fw",
"DSCopeU3P100.bin",
"DSCopeU3P100.bin",
{CAPS_MODE_ANALOG | CAPS_MODE_DSO,
CAPS_FEATURE_ZERO | CAPS_FEATURE_FLASH | CAPS_FEATURE_USB30 | CAPS_FEATURE_HMCAD1511 | CAPS_FEATURE_20M,
(1 << DSL_ANALOG10x2_500) |
(1 << DSL_DSO1000x2),
2,
SR_GB(2),
SR_Mn(2),
0,
vdivs10to2000,
samplerates1000,
4,
DSL_DSO1000x2,
SR_MHZ(500),
SR_Mn(1),
900,
1024-900,
10,
245,
60,
SR_HZ(0),
SR_HZ(0)}
},
{0x2A0E, 0x002B, LIBUSB_SPEED_SUPER, "DreamSourceLab", "DSCope U3P100", NULL,
"DSCopeU3P100.fw",
"DSCopeU3P100.bin",
"DSCopeU3P100.bin",
{CAPS_MODE_ANALOG | CAPS_MODE_DSO,
CAPS_FEATURE_ZERO | CAPS_FEATURE_FLASH | CAPS_FEATURE_USB30 | CAPS_FEATURE_HMCAD1511 | CAPS_FEATURE_20M,
(1 << DSL_ANALOG10x2_500) |
(1 << DSL_DSO1000x2),
2,
SR_GB(2),
SR_Mn(2),
0,
vdivs10to2000,
samplerates1000,
4,
DSL_DSO1000x2,
SR_MHZ(500),
SR_Mn(1),
900,
1024-900,
10,
245,
60,
SR_HZ(0),
SR_HZ(0)}
},
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}
};
......@@ -880,6 +1121,9 @@ struct DSL_context {
int16_t tune_index;
int zero_stage;
int zero_pcnt;
gboolean zero_branch;
gboolean zero_comb_fgain;
gboolean zero_comb;
int tune_stage;
int tune_pcnt;
struct sr_channel *tune_probe;
......@@ -908,6 +1152,7 @@ struct DSL_context {
gboolean abort;
gboolean overflow;
int bw_limit;
int empty_poll_count;
int language;
};
......@@ -1085,6 +1330,13 @@ SR_PRIV int dsl_rd_nvm(const struct sr_dev_inst *sdi, unsigned char *ctx, uint16
SR_PRIV int dsl_rd_probe(const struct sr_dev_inst *sdi, unsigned char *ctx, uint16_t addr, uint8_t len);
SR_PRIV int dsl_config_adc(const struct sr_dev_inst *sdi, const struct DSL_adc_config *config);
SR_PRIV double dsl_adc_code2fgain(uint8_t code);
SR_PRIV uint8_t dsl_adc_fgain2code(double gain);
SR_PRIV int dsl_config_adc_fgain(const struct sr_dev_inst *sdi, uint8_t branch, double gain0, double gain1);
SR_PRIV int dsl_config_fpga_fgain(const struct sr_dev_inst *sdi);
SR_PRIV int dsl_skew_fpga_fgain(const struct sr_dev_inst *sdi, gboolean comb, double skew[]);
SR_PRIV int dsl_probe_cali_fgain(struct DSL_context *devc, struct sr_channel *probe, double mean, gboolean comb, gboolean reset);
SR_PRIV gboolean dsl_probe_fgain_inrange(struct sr_channel *probe, gboolean comb, double skew[]);
SR_PRIV int dsl_fpga_arm(const struct sr_dev_inst *sdi);
SR_PRIV int dsl_fpga_config(struct libusb_device_handle *hdl, const char *filename);
......@@ -1101,7 +1353,7 @@ SR_PRIV int dsl_config_list(int key, GVariant **data, const struct sr_dev_inst *
SR_PRIV int dsl_dev_open(struct sr_dev_driver *di, struct sr_dev_inst *sdi, gboolean *fpga_done);
SR_PRIV int dsl_dev_close(struct sr_dev_inst *sdi);
SR_PRIV int dsl_dev_acquisition_stop(const struct sr_dev_inst *sdi, void *cb_data);
SR_PRIV int dsl_dev_status_get(const struct sr_dev_inst *sdi, struct sr_status *status, gboolean prg, int begin, int end);
SR_PRIV int dsl_dev_status_get(const struct sr_dev_inst *sdi, struct sr_status *status, gboolean prg);
SR_PRIV unsigned int dsl_get_timeout(const struct sr_dev_inst *sdi);
SR_PRIV int dsl_start_transfers(const struct sr_dev_inst *sdi);
......
libsigrok4DSL/hardware/DSL/dslogic.c
View file @ a5f47b42
......@@ -228,6 +228,9 @@ static struct DSL_context *DSLogic_dev_new(const struct DSL_profile *prof)
devc->trigger_hrate = 0;
devc->trigger_holdoff = 0;
devc->zero = FALSE;
devc->zero_branch = FALSE;
devc->zero_comb_fgain = FALSE;
devc->zero_comb = FALSE;
devc->status = DSL_FINISH;
devc->mstatus_valid = FALSE;
......@@ -932,7 +935,7 @@ static int config_set(int id, GVariant *data, struct sr_dev_inst *sdi,
dsl_adjust_samplerate(devc);
if (devc->op_mode == OP_INTEST) {
devc->cur_samplerate = devc->stream ? channel_modes[devc->ch_mode].max_samplerate / 10 :
channel_modes[devc->ch_mode].max_samplerate;
SR_MHZ(100);
devc->limit_samples = devc->stream ? devc->cur_samplerate * 3 :
devc->profile->dev_caps.hw_depth / dsl_en_ch_num(sdi);
}
......@@ -1042,10 +1045,6 @@ static int config_set(int id, GVariant *data, struct sr_dev_inst *sdi,
ch->offset = g_variant_get_uint16(data);
sr_dbg("%s: setting OFFSET of channel %d to %d", __func__,
ch->index, ch->offset);
} else if (id == SR_CONF_PROBE_HW_OFFSET) {
ch->hw_offset = g_variant_get_uint16(data);
sr_dbg("%s: setting OFFSET of channel %d to %d", __func__,
ch->index, ch->offset);
} else if (id == SR_CONF_TRIGGER_SOURCE) {
devc->trigger_source = g_variant_get_byte(data);
if (sdi->mode == DSO) {
......@@ -1119,12 +1118,12 @@ static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi,
for (i = 0; i < ARRAY_SIZE(channel_modes); i++) {
if (channel_modes[i].stream == devc->stream &&
devc->profile->dev_caps.channels & (1 << i)) {
if (devc->test_mode != SR_TEST_NONE && devc->profile->dev_caps.intest_channel != channel_modes[i].id)
continue;
if (devc->language == LANGUAGE_CN)
g_variant_builder_add(&gvb, "s", channel_modes[i].descr_cn);
else
g_variant_builder_add(&gvb, "s", channel_modes[i].descr);
if (devc->test_mode != SR_TEST_NONE)
break;
}
}
*data = g_variant_builder_end(&gvb);
......@@ -1197,6 +1196,17 @@ static void remove_sources(struct DSL_context *devc)
g_free(devc->usbfd);
}
static void report_overflow(struct DSL_context *devc)
{
struct sr_datafeed_packet packet;
struct sr_dev_inst *sdi = devc->cb_data;
packet.status = SR_PKT_OK;
packet.type = SR_DF_OVERFLOW;
packet.payload = NULL;
sr_session_send(sdi, &packet);
}
static int receive_data(int fd, int revents, const struct sr_dev_inst *sdi)
{
int completed = 0;
......@@ -1218,16 +1228,44 @@ static int receive_data(int fd, int revents, const struct sr_dev_inst *sdi)
tv.tv_sec = tv.tv_usec = 0;
libusb_handle_events_timeout_completed(drvc->sr_ctx->libusb_ctx, &tv, &completed);
// overflow check
if (devc->stream && devc->trf_completed) {
rd_cmd.header.dest = DSL_CTL_HW_STATUS;
rd_cmd.header.size = 1;
hw_info = 0;
rd_cmd.data = &hw_info;
if (devc->trf_completed)
devc->empty_poll_count = 0;
else
devc->empty_poll_count++;
// --
// progress check
// must before overflow check (1ch@10K)
// --
if ((devc->empty_poll_count > MAX_EMPTY_POLL) && (devc->status == DSL_START)) {
devc->mstatus.captured_cnt0 = 0;
rd_cmd.header.dest = DSL_CTL_I2C_STATUS;
rd_cmd.header.offset = 0;
rd_cmd.header.size = 4;
rd_cmd.data = (unsigned char*)&devc->mstatus;
if ((ret = command_ctl_rd(usb->devhdl, rd_cmd)) != SR_OK)
sr_err("Failed to get hardware infos.");
else
devc->overflow = (hw_info & bmSYS_OVERFLOW) != 0;
sr_err("Failed to get progress infos.");
devc->empty_poll_count = 0;
}
// overflow check
if (devc->stream) {
if (devc->empty_poll_count > MAX_EMPTY_POLL) {
rd_cmd.header.dest = DSL_CTL_HW_STATUS;
rd_cmd.header.size = 1;
hw_info = 0;
rd_cmd.data = &hw_info;
if ((ret = command_ctl_rd(usb->devhdl, rd_cmd)) != SR_OK)
sr_err("Failed to get hardware infos.");
else
devc->overflow = (hw_info & bmSYS_OVERFLOW) != 0;
if (devc->overflow)
report_overflow(devc);
devc->empty_poll_count = 0;
}
}
if (devc->status == DSL_FINISH) {
......@@ -1263,13 +1301,19 @@ static int dev_acquisition_start(struct sr_dev_inst *sdi, void *cb_data)
devc->num_samples = 0;
devc->num_bytes = 0;
devc->empty_transfer_count = 0;
devc->empty_poll_count = 0;
devc->status = DSL_INIT;
devc->num_transfers = 0;
devc->submitted_transfers = 0;
devc->actual_samples = (devc->limit_samples + 1023ULL) & ~1023ULL;
devc->actual_samples = (devc->limit_samples + SAMPLES_ALIGN) & ~SAMPLES_ALIGN;
devc->actual_bytes = devc->actual_samples / DSLOGIC_ATOMIC_SAMPLES * dsl_en_ch_num(sdi) * DSLOGIC_ATOMIC_SIZE;
devc->abort = FALSE;
devc->mstatus_valid = FALSE;
devc->mstatus.captured_cnt0 = 0;
devc->mstatus.captured_cnt1 = 0;
devc->mstatus.captured_cnt2 = 0;
devc->mstatus.captured_cnt3 = 0;
devc->mstatus.trig_hit = 0;
devc->overflow = FALSE;
/* Configures devc->trigger_* and devc->sample_wide */
......@@ -1346,9 +1390,9 @@ static int dev_acquisition_stop(const struct sr_dev_inst *sdi, void *cb_data)
return ret;
}
static int dev_status_get(const struct sr_dev_inst *sdi, struct sr_status *status, gboolean prg, int begin, int end)
static int dev_status_get(const struct sr_dev_inst *sdi, struct sr_status *status, gboolean prg)
{
int ret = dsl_dev_status_get(sdi, status, prg, begin, end);
int ret = dsl_dev_status_get(sdi, status, prg);
return ret;
}
......
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