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Raptor Engineering Public Development
dsview
Commits
771f2c56
Commit
771f2c56
authored
4 years ago
by
DreamSourceLab
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Plain Diff
fix some decoder issues
parent
dd4454e9
Changes
3
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Showing
3 changed files
with
37 additions
and
17 deletions
+37
-17
libsigrokdecode4DSL/decoders/dmx512/pd.py
libsigrokdecode4DSL/decoders/dmx512/pd.py
+7
-6
libsigrokdecode4DSL/decoders/rgb_led_ws281x/pd.py
libsigrokdecode4DSL/decoders/rgb_led_ws281x/pd.py
+29
-10
libsigrokdecode4DSL/decoders/swim/pd.py
libsigrokdecode4DSL/decoders/swim/pd.py
+1
-1
No files found.
libsigrokdecode4DSL/decoders/dmx512/pd.py
View file @
771f2c56
...
...
@@ -82,7 +82,7 @@ class Decoder(srd.Decoder):
raise
SamplerateError
(
'Cannot decode without samplerate.'
)
inv
=
self
.
options
[
'invert'
]
==
'yes'
while
True
:
# Seek for an interval with no state change with a length between
# 88 and 1000000 us (BREAK).
...
...
@@ -111,7 +111,7 @@ class Decoder(srd.Decoder):
# Mark and read a single transmitted byte
# (start bit, 8 data bits, 2 stop bits).
elif
self
.
state
==
'READ BYTE'
:
bit_start
=
self
.
samplenum
bit_start
=
self
.
samplenum
bit_end
=
self
.
run_start
+
(
self
.
bit
+
1
)
*
self
.
skip_per_bit
(
dmx
,)
=
self
.
wait
({
'skip'
:
round
(
self
.
skip_per_bit
/
2
)})
bit_value
=
not
dmx
if
inv
else
dmx
...
...
@@ -136,7 +136,7 @@ class Decoder(srd.Decoder):
self
.
state
=
'FIND BREAK'
else
:
# Label and process one bit.
self
.
put
(
bit_start
,
bit_end
,
self
.
put
(
bit_start
,
bit_end
,
self
.
out_ann
,
[
0
,
[
str
(
bit_value
)]])
self
.
byte
|=
bit_value
<<
(
self
.
bit
-
1
)
...
...
@@ -161,14 +161,15 @@ class Decoder(srd.Decoder):
# Mark the INTERFRAME-TIME between bytes / INTERPACKET-TIME between packets.
elif
self
.
state
==
'MARK IFT'
:
self
.
run_start
=
self
.
samplenum
(
dmx
,)
=
self
.
wait
({
0
:
'l'
if
inv
else
'h'
})
(
dmx
,)
=
self
.
wait
({
0
:
'r'
if
inv
else
'f'
})
if
self
.
channel
>
512
:
(
dmx
,)
=
self
.
wait
({
0
:
'h'
if
inv
else
'l'
})
self
.
putr
([
8
,
[
'Interpacket'
]])
self
.
state
=
'FIND BREAK'
self
.
run_start
=
self
.
samplenum
else
:
self
.
putr
([
7
,
[
'Interframe'
]])
if
(
not
dmx
if
inv
else
dmx
):
(
dmx
,)
=
self
.
wait
({
0
:
'h'
if
inv
else
'l'
})
self
.
putr
([
7
,
[
'Interframe'
]])
self
.
state
=
'READ BYTE'
self
.
bit
=
0
self
.
run_start
=
self
.
samplenum
This diff is collapsed.
Click to expand it.
libsigrokdecode4DSL/decoders/rgb_led_ws281x/pd.py
View file @
771f2c56
...
...
@@ -57,6 +57,7 @@ class Decoder(srd.Decoder):
self
.
ss
=
None
self
.
es
=
None
self
.
bits
=
[]
self
.
bit_
=
None
def
start
(
self
):
self
.
out_ann
=
self
.
register
(
srd
.
OUTPUT_ANN
)
...
...
@@ -74,18 +75,35 @@ class Decoder(srd.Decoder):
self
.
bits
=
[]
self
.
ss_packet
=
samplenum
def
check_bit_
(
self
,
samplenum
):
period
=
samplenum
-
self
.
ss
tH_samples
=
self
.
es
-
self
.
ss
tH
=
tH_samples
/
self
.
samplerate
if
tH
>=
625e-9
:
self
.
bit_
=
True
else
:
# Ideal duty for T0H: 33%, T1H: 66%.
self
.
bit_
=
(
tH_samples
/
period
)
>
0.5
def
decode
(
self
):
if
not
self
.
samplerate
:
raise
SamplerateError
(
'Cannot decode without samplerate.'
)
while
True
:
if
self
.
state
==
'FIND RESET'
:
self
.
wait
({
0
:
'
f
'
})
self
.
wait
({
0
:
'
l
'
})
self
.
ss
=
self
.
samplenum
self
.
wait
({
0
:
'r'
})
self
.
es
=
self
.
samplenum
if
((
self
.
es
-
self
.
ss
)
/
self
.
samplerate
>
50e-6
):
self
.
state
=
'RESET'
elif
((
self
.
es
-
self
.
ss
)
/
self
.
samplerate
>
3e-6
):
self
.
bits
=
[]
self
.
ss
=
self
.
samplenum
self
.
ss_packet
=
self
.
samplenum
self
.
wait
({
0
:
'f'
})
self
.
state
=
'BIT FALLING'
elif
self
.
state
==
'RESET'
:
self
.
put
(
self
.
ss
,
self
.
es
,
self
.
out_ann
,
[
1
,
[
'RESET'
,
'RST'
,
'R'
]])
self
.
bits
=
[]
...
...
@@ -96,22 +114,23 @@ class Decoder(srd.Decoder):
elif
self
.
state
==
'BIT FALLING'
:
self
.
es
=
self
.
samplenum
self
.
wait
({
0
:
'r'
})
if
((
self
.
es
-
self
.
ss
)
/
self
.
samplerate
>
50e-6
):
if
((
self
.
samplenum
-
self
.
es
)
/
self
.
samplerate
>
50e-6
):
self
.
check_bit_
(
self
.
samplenum
)
self
.
put
(
self
.
ss
,
self
.
es
,
self
.
out_ann
,
[
0
,
[
'%d'
%
self
.
bit_
]])
self
.
bits
.
append
(
self
.
bit_
)
self
.
handle_bits
(
self
.
es
)
self
.
ss
=
self
.
es
self
.
es
=
self
.
samplenum
self
.
state
=
'RESET'
else
:
self
.
state
=
'BIT RISING'
elif
self
.
state
==
'BIT RISING'
:
period
=
self
.
samplenum
-
self
.
ss
duty
=
self
.
es
-
self
.
ss
# Ideal duty for T0H: 33%, T1H: 66%.
bit_
=
(
duty
/
period
)
>
0.5
self
.
check_bit_
(
self
.
samplenum
)
self
.
put
(
self
.
ss
,
self
.
samplenum
,
self
.
out_ann
,
[
0
,
[
'%d'
%
bit_
]])
self
.
bits
.
append
(
bit_
)
[
0
,
[
'%d'
%
self
.
bit_
]])
self
.
bits
.
append
(
self
.
bit_
)
self
.
handle_bits
(
self
.
samplenum
)
self
.
ss
=
self
.
samplenum
...
...
This diff is collapsed.
Click to expand it.
libsigrokdecode4DSL/decoders/swim/pd.py
View file @
771f2c56
...
...
@@ -297,7 +297,7 @@ class Decoder(srd.Decoder):
if
self
.
bit_edge
[
1
][
0
]
!=
0
and
swim
==
0
:
self
.
bit_maxlen
=
self
.
bit_reflen
if
self
.
bit_edge
[
0
][
0
]
==
0
and
self
.
bit_edge
[
1
][
0
]
==
1
and
self
.
samplenum
-
self
.
bit_edge
[
0
][
1
]
<=
self
.
bit_reflen
+
2
:
if
self
.
bit_edge
[
0
][
0
]
==
0
and
self
.
bit_edge
[
1
][
0
]
==
1
and
self
.
samplenum
-
self
.
bit_edge
[
0
][
1
]
<=
self
.
bit_reflen
+
10
:
self
.
bit
(
self
.
bit_edge
[
0
][
1
],
self
.
bit_edge
[
1
][
1
],
self
.
samplenum
)
self
.
bit_edge
.
pop
(
0
)
...
...
This diff is collapsed.
Click to expand it.
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