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Commit 7328b0b2 authored by DreamSourceLab's avatar DreamSourceLab
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Add 32 channels trigger support

parent caad2393
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Showing with 779 additions and 369 deletions
DSView/pv/dock/triggerdock.cpp
View file @ 7328b0b2
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DSView/pv/dock/triggerdock.h
View file @ 7328b0b2
......@@ -78,6 +78,9 @@ private:
void retranslateUi();
void reStyle();
void setup_adv_tab();
void lineEdit_highlight(QLineEdit *dst);
signals:
public slots:
......@@ -94,6 +97,7 @@ private:
private:
SigSession &_session;
int _cur_ch_num;
QWidget *_widget;
QRadioButton *_simple_radioButton;
......@@ -112,9 +116,11 @@ private:
QVector <QLabel *> _mu_label_list;
QVector <QComboBox *> _logic_comboBox_list;
QVector <QLineEdit *> _value0_lineEdit_list;
QVector <QLineEdit *> _value0_ext32_lineEdit_list;
QVector <QSpinBox *> _count_spinBox_list;
QVector <QComboBox *> _inv0_comboBox_list;
QVector <QLineEdit *> _value1_lineEdit_list;
QVector <QLineEdit *> _value1_ext32_lineEdit_list;
QVector <QComboBox *> _inv1_comboBox_list;
QVector <QCheckBox *> _contiguous_checkbox_list;
......@@ -122,10 +128,13 @@ private:
QGroupBox *_serial_groupBox;
QLabel *_serial_start_label;
QLineEdit *_serial_start_lineEdit;
QLineEdit *_serial_start_ext32_lineEdit;
QLabel *_serial_stop_label;
QLineEdit *_serial_stop_lineEdit;
QLineEdit *_serial_stop_ext32_lineEdit;
QLabel *_serial_edge_label;
QLineEdit *_serial_edge_lineEdit;
QLineEdit *_serial_edge_ext32_lineEdit;
QLabel *_serial_data_label;
QComboBox *_serial_data_comboBox;
QLabel *_serial_value_label;
......
DSView/res/DSCope.bin
View file @ 7328b0b2
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DSView/res/DSCope20.bin
View file @ 7328b0b2
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DSView/res/DSLogic33.bin
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DSView/res/DSLogic50.bin
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libsigrok4DSL/hardware/DSL/dsl.c
View file @ 7328b0b2
This diff is collapsed.
libsigrok4DSL/hardware/DSL/dsl.h
View file @ 7328b0b2
......@@ -83,7 +83,13 @@
// use ADF4360-7 vco chip
#define CAPS_FEATURE_ADF4360 (1 << 8)
// 20M bandwidth limitation
#define CAPS_FEATURE_20M (1 << 8)
#define CAPS_FEATURE_20M (1 << 9)
// use startup flash (fx3)
#define CAPS_FEATURE_FLASH (1 << 10)
// 32 channels
#define CAPS_FEATURE_LA_CH32 (1 << 11)
// auto tunning vgain
#define CAPS_FEATURE_AUTO_VGAIN (1 << 12)
/* end */
......@@ -156,6 +162,7 @@ struct DSL_caps {
uint64_t mode_caps;
uint64_t feature_caps;
uint64_t channels;
uint64_t total_ch_num;
uint64_t hw_depth;
uint64_t dso_depth;
uint8_t intest_channel;
......@@ -170,6 +177,8 @@ struct DSL_caps {
uint32_t ref_min;
uint32_t ref_max;
uint16_t default_comb_comp;
uint64_t half_samplerate;
uint64_t quarter_samplerate;
};
struct DSL_profile {
......@@ -442,6 +451,7 @@ static const struct DSL_profile supported_DSLogic[] = {
(1 << DSL_BUFFER100x16) | (1 << DSL_BUFFER200x8) | (1 << DSL_BUFFER400x4) |
(1 << DSL_ANALOG10x2) |
(1 << DSL_DSO200x2),
16,
SR_MB(256),
SR_Mn(2),
DSL_BUFFER100x16,
......@@ -455,7 +465,9 @@ static const struct DSL_profile supported_DSLogic[] = {
0,
0,
0,
0}
0,
SR_MHZ(200),
SR_MHZ(400)}
},
{0x2A0E, 0x0003, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSLogic Pro", NULL,
......@@ -466,6 +478,7 @@ static const struct DSL_profile supported_DSLogic[] = {
CAPS_FEATURE_SEEP | CAPS_FEATURE_VTH | CAPS_FEATURE_BUF,
(1 << DSL_STREAM20x16) | (1 << DSL_STREAM25x12) | (1 << DSL_STREAM50x6) | (1 << DSL_STREAM100x3) |
(1 << DSL_BUFFER100x16) | (1 << DSL_BUFFER200x8) | (1 << DSL_BUFFER400x4),
16,
SR_MB(256),
0,
DSL_BUFFER100x16,
......@@ -479,7 +492,9 @@ static const struct DSL_profile supported_DSLogic[] = {
0,
0,
0,
0}
0,
SR_MHZ(200),
SR_MHZ(400)}
},
{0x2A0E, 0x0020, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSLogic PLus", NULL,
......@@ -490,6 +505,7 @@ static const struct DSL_profile supported_DSLogic[] = {
CAPS_FEATURE_VTH | CAPS_FEATURE_BUF,
(1 << DSL_STREAM20x16) | (1 << DSL_STREAM25x12) | (1 << DSL_STREAM50x6) | (1 << DSL_STREAM100x3) |
(1 << DSL_BUFFER100x16) | (1 << DSL_BUFFER200x8) | (1 << DSL_BUFFER400x4),
16,
SR_MB(256),
0,
DSL_BUFFER100x16,
......@@ -503,7 +519,9 @@ static const struct DSL_profile supported_DSLogic[] = {
0,
0,
0,
0}
0,
SR_MHZ(200),
SR_MHZ(400)}
},
{0x2A0E, 0x0021, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSLogic Basic", NULL,
......@@ -514,6 +532,7 @@ static const struct DSL_profile supported_DSLogic[] = {
CAPS_FEATURE_VTH,
(1 << DSL_STREAM20x16) | (1 << DSL_STREAM25x12) | (1 << DSL_STREAM50x6) | (1 << DSL_STREAM100x3) |
(1 << DSL_BUFFER100x16) | (1 << DSL_BUFFER200x8) | (1 << DSL_BUFFER400x4),
16,
SR_KB(256),
0,
DSL_STREAM20x16,
......@@ -527,7 +546,9 @@ static const struct DSL_profile supported_DSLogic[] = {
0,
0,
0,
0}
0,
SR_MHZ(200),
SR_MHZ(400)}
},
{0x2A0E, 0x0029, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSLogic U2Basic", NULL,
......@@ -538,6 +559,7 @@ static const struct DSL_profile supported_DSLogic[] = {
CAPS_FEATURE_VTH | CAPS_FEATURE_BUF,
(1 << DSL_STREAM20x16) | (1 << DSL_STREAM25x12) | (1 << DSL_STREAM50x6) | (1 << DSL_STREAM100x3) |
(1 << DSL_BUFFER100x16),
16,
SR_MB(64),
0,
DSL_BUFFER100x16,
......@@ -551,10 +573,12 @@ static const struct DSL_profile supported_DSLogic[] = {
0,
0,
0,
0}
0,
SR_MHZ(200),
SR_MHZ(400)}
},
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}
};
static const struct DSL_profile supported_DSCope[] = {
......@@ -569,6 +593,7 @@ static const struct DSL_profile supported_DSCope[] = {
CAPS_FEATURE_ZERO | CAPS_FEATURE_PREOFF | CAPS_FEATURE_SEEP | CAPS_FEATURE_BUF,
(1 << DSL_ANALOG10x2) |
(1 << DSL_DSO200x2),
2,
SR_MB(256),
SR_Mn(2),
0,
......@@ -582,7 +607,9 @@ static const struct DSL_profile supported_DSCope[] = {
1024-920,
1,
255,
0}
0,
SR_HZ(0),
SR_HZ(0)}
},
{0x2A0E, 0x0004, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSCope20", NULL,
......@@ -593,6 +620,7 @@ static const struct DSL_profile supported_DSCope[] = {
CAPS_FEATURE_ZERO | CAPS_FEATURE_SEEP | CAPS_FEATURE_BUF,
(1 << DSL_ANALOG10x2) |
(1 << DSL_DSO200x2),
2,
SR_MB(256),
SR_Mn(2),
0,
......@@ -606,7 +634,9 @@ static const struct DSL_profile supported_DSCope[] = {
1024-920,
1,
255,
0}
0,
SR_HZ(0),
SR_HZ(0)}
},
{0x2A0E, 0x0022, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSCope B20", NULL,
......@@ -617,6 +647,7 @@ static const struct DSL_profile supported_DSCope[] = {
CAPS_FEATURE_ZERO | CAPS_FEATURE_BUF,
(1 << DSL_ANALOG10x2) |
(1 << DSL_DSO200x2),
2,
SR_MB(256),
SR_Mn(2),
0,
......@@ -630,7 +661,9 @@ static const struct DSL_profile supported_DSCope[] = {
1024-920,
1,
255,
0}
0,
SR_HZ(0),
SR_HZ(0)}
},
{0x2A0E, 0x0023, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSCope C20", NULL,
......@@ -641,6 +674,7 @@ static const struct DSL_profile supported_DSCope[] = {
CAPS_FEATURE_ZERO | CAPS_FEATURE_BUF,
(1 << DSL_ANALOG10x2) |
(1 << DSL_DSO200x2),
2,
SR_MB(256),
SR_Mn(2),
0,
......@@ -654,7 +688,9 @@ static const struct DSL_profile supported_DSCope[] = {
1024-920,
1,
255,
0}
0,
SR_HZ(0),
SR_HZ(0)}
},
......@@ -666,6 +702,7 @@ static const struct DSL_profile supported_DSCope[] = {
CAPS_FEATURE_ZERO | CAPS_FEATURE_BUF | CAPS_FEATURE_POGOPIN,
(1 << DSL_ANALOG10x2) |
(1 << DSL_DSO200x2),
2,
SR_MB(256),
SR_Mn(2),
0,
......@@ -679,7 +716,9 @@ static const struct DSL_profile supported_DSCope[] = {
1024-920,
1,
255,
0}
0,
SR_HZ(0),
SR_HZ(0)}
},
{0x2A0E, 0x0025, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSCope C20", NULL,
......@@ -690,6 +729,7 @@ static const struct DSL_profile supported_DSCope[] = {
CAPS_FEATURE_ZERO,
(1 << DSL_ANALOG10x2) |
(1 << DSL_DSO200x2),
2,
SR_KB(256),
SR_Kn(20),
0,
......@@ -703,7 +743,9 @@ static const struct DSL_profile supported_DSCope[] = {
1024-920,
1,
255,
0}
0,
SR_HZ(0),
SR_HZ(0)}
},
{0x2A0E, 0x0026, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSCope U2B20", NULL,
......@@ -714,6 +756,7 @@ static const struct DSL_profile supported_DSCope[] = {
CAPS_FEATURE_ZERO,
(1 << DSL_ANALOG10x2) |
(1 << DSL_DSO200x2),
2,
SR_KB(256),
SR_Kn(20),
0,
......@@ -727,7 +770,9 @@ static const struct DSL_profile supported_DSCope[] = {
1024-945,
10,
245,
22}
22,
SR_HZ(0),
SR_HZ(0)}
},
{0x2A0E, 0x0027, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSCope U2P20", NULL,
......@@ -738,6 +783,7 @@ static const struct DSL_profile supported_DSCope[] = {
CAPS_FEATURE_ZERO | CAPS_FEATURE_BUF | CAPS_FEATURE_POGOPIN,
(1 << DSL_ANALOG10x2) |
(1 << DSL_DSO200x2),
2,
SR_MB(256),
SR_Mn(2),
0,
......@@ -751,11 +797,13 @@ static const struct DSL_profile supported_DSCope[] = {
1024-945,
10,
245,
22}
22,
SR_HZ(0),
SR_HZ(0)}
},
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}
};
static const gboolean default_ms_en[] = {
......@@ -883,12 +931,14 @@ struct DSL_setting {
uint16_t tpos_h;
uint16_t trig_glb_header; // 7
uint16_t trig_glb;
uint16_t ch_en_header; // 8
uint16_t ch_en;
uint16_t dso_count_header; // 9-10
uint16_t dso_count_header; // 8-9
uint16_t dso_cnt_l;
uint16_t dso_cnt_h;
uint16_t misc_align;
uint16_t ch_en_header; // 10-11
uint16_t ch_en_l;
uint16_t ch_en_h;
uint16_t fgain_header; // 12
uint16_t fgain;
uint16_t trig_header; // 64
uint16_t trig_mask0[NUM_TRIGGER_STAGES];
......@@ -904,6 +954,21 @@ struct DSL_setting {
uint32_t end_sync;
};
struct DSL_setting_ext32 {
uint32_t sync;
uint16_t trig_header; // 96
uint16_t trig_mask0[NUM_TRIGGER_STAGES];
uint16_t trig_mask1[NUM_TRIGGER_STAGES];
uint16_t trig_value0[NUM_TRIGGER_STAGES];
uint16_t trig_value1[NUM_TRIGGER_STAGES];
uint16_t trig_edge0[NUM_TRIGGER_STAGES];
uint16_t trig_edge1[NUM_TRIGGER_STAGES];
uint16_t align_bytes;
uint32_t end_sync;
};
struct DSL_adc_config {
uint8_t dest;
uint8_t cnt;
......
libsigrok4DSL/hardware/DSL/dslogic.c
View file @ 7328b0b2
......@@ -662,6 +662,11 @@ static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi,
return SR_ERR;
*data = g_variant_new_int16(channel_modes[devc->ch_mode].vld_num);
break;
case SR_CONF_TOTAL_CH_NUM:
if (!sdi)
return SR_ERR;
*data = g_variant_new_int16(devc->profile->dev_caps.total_ch_num);
break;
default:
return SR_ERR_NA;
}
......
libsigrok4DSL/libsigrok.h
View file @ 7328b0b2
......@@ -118,6 +118,7 @@ enum {
#define DS_MAX_DSO_PROBES_NUM 2
#define TriggerStages 16
#define TriggerProbes 16
#define MaxTriggerProbes 32
#define TriggerCountBits 16
#define STriggerDataStage 3
......@@ -857,9 +858,15 @@ enum {
SR_CONF_REF_MIN,
SR_CONF_REF_MAX,
/** Valid channel number */
SR_CONF_TOTAL_CH_NUM,
/** Valid channel number */
SR_CONF_VLD_CH_NUM,
/** 32 channel support */
SR_CONF_LA_CH32,
/** Zero */
SR_CONF_HAVE_ZERO,
SR_CONF_ZERO,
......@@ -1254,8 +1261,8 @@ struct ds_trigger {
unsigned char trigger_logic[TriggerStages+1];
unsigned char trigger0_inv[TriggerStages+1];
unsigned char trigger1_inv[TriggerStages+1];
char trigger0[TriggerStages+1][TriggerProbes];
char trigger1[TriggerStages+1][TriggerProbes];
char trigger0[TriggerStages+1][MaxTriggerProbes];
char trigger1[TriggerStages+1][MaxTriggerProbes];
uint32_t trigger0_count[TriggerStages+1];
uint32_t trigger1_count[TriggerStages+1];
};
......
libsigrok4DSL/proto.h
View file @ 7328b0b2
......@@ -173,10 +173,10 @@ SR_API int ds_trigger_set_en(uint16_t enable);
SR_API uint16_t ds_trigger_get_en();
SR_API int ds_trigger_set_mode(uint16_t mode);
SR_PRIV uint64_t ds_trigger_get_mask0(uint16_t stage);
SR_PRIV uint64_t ds_trigger_get_value0(uint16_t stage);
SR_PRIV uint64_t ds_trigger_get_edge0(uint16_t stage);
SR_PRIV uint64_t ds_trigger_get_mask1(uint16_t stage);
SR_PRIV uint64_t ds_trigger_get_value1(uint16_t stage);
SR_PRIV uint64_t ds_trigger_get_edge1(uint16_t stage);
SR_PRIV uint16_t ds_trigger_get_mask0(uint16_t stage, uint16_t msc, uint16_t lsc, gboolean qutr_mode, gboolean half_mode);
SR_PRIV uint16_t ds_trigger_get_value0(uint16_t stage, uint16_t msc, uint16_t lsc, gboolean qutr_mode, gboolean half_mode);
SR_PRIV uint16_t ds_trigger_get_edge0(uint16_t stage, uint16_t msc, uint16_t lsc, gboolean qutr_mode, gboolean half_mode);
SR_PRIV uint16_t ds_trigger_get_mask1(uint16_t stage, uint16_t msc, uint16_t lsc, gboolean qutr_mode, gboolean half_mode);
SR_PRIV uint16_t ds_trigger_get_value1(uint16_t stage, uint16_t msc, uint16_t lsc, gboolean qutr_mode, gboolean half_mode);
SR_PRIV uint16_t ds_trigger_get_edge1(uint16_t stage, uint16_t msc, uint16_t lsc, gboolean qutr_mode, gboolean half_mode);
#endif
libsigrok4DSL/trigger.c
View file @ 7328b0b2
......@@ -58,7 +58,7 @@ SR_API int ds_trigger_init(void)
trigger->trigger_stages = 0;
for (i = 0; i <= TriggerStages; i++) {
for (j = 0; j < TriggerProbes; j++) {
for (j = 0; j < MaxTriggerProbes; j++) {
trigger->trigger0[i][j] = 'X';
trigger->trigger1[i][j] = 'X';
}
......@@ -99,7 +99,7 @@ SR_API struct ds_trigger *ds_trigger_get(void)
SR_API int ds_trigger_stage_set_value(uint16_t stage, uint16_t probes, char *trigger0, char *trigger1)
{
assert(stage < TriggerStages);
assert(probes <= TriggerProbes);
assert(probes <= MaxTriggerProbes);
int j;
......@@ -113,7 +113,7 @@ SR_API int ds_trigger_stage_set_value(uint16_t stage, uint16_t probes, char *tri
SR_API int ds_trigger_stage_set_logic(uint16_t stage, uint16_t probes, unsigned char trigger_logic)
{
assert(stage < TriggerStages);
assert(probes <= TriggerProbes);
assert(probes <= MaxTriggerProbes);
trigger->trigger_logic[stage] = trigger_logic;
......@@ -122,7 +122,7 @@ SR_API int ds_trigger_stage_set_logic(uint16_t stage, uint16_t probes, unsigned
SR_API int ds_trigger_stage_set_inv(uint16_t stage, uint16_t probes, unsigned char trigger0_inv, unsigned char trigger1_inv)
{
assert(stage < TriggerStages);
assert(probes <= TriggerProbes);
assert(probes <= MaxTriggerProbes);
trigger->trigger0_inv[stage] = trigger0_inv;
trigger->trigger1_inv[stage] = trigger1_inv;
......@@ -132,7 +132,7 @@ SR_API int ds_trigger_stage_set_inv(uint16_t stage, uint16_t probes, unsigned ch
SR_API int ds_trigger_stage_set_count(uint16_t stage, uint16_t probes, uint32_t trigger0_count, uint32_t trigger1_count)
{
assert(stage < TriggerStages);
assert(probes <= TriggerProbes);
assert(probes <= MaxTriggerProbes);
trigger->trigger0_count[stage] = trigger0_count;
trigger->trigger1_count[stage] = trigger1_count;
......@@ -147,7 +147,7 @@ SR_API int ds_trigger_stage_set_count(uint16_t stage, uint16_t probes, uint32_t
*/
SR_API int ds_trigger_probe_set(uint16_t probe, unsigned char trigger0, unsigned char trigger1)
{
assert(probe < TriggerProbes);
assert(probe < MaxTriggerProbes);
trigger->trigger0[TriggerStages][probe] = trigger0;
trigger->trigger1[TriggerStages][probe] = trigger1;
......@@ -235,90 +235,168 @@ SR_API int ds_trigger_set_mode(uint16_t mode)
/*
*
*/
SR_PRIV uint64_t ds_trigger_get_mask0(uint16_t stage)
SR_PRIV uint16_t ds_trigger_get_mask0(uint16_t stage, uint16_t msc, uint16_t lsc, gboolean qutr_mode, gboolean half_mode)
{
assert(stage <= TriggerStages);
assert(lsc <= msc);
assert(msc < MaxTriggerProbes);
uint64_t mask = 0;
uint16_t mask = 0;
const uint16_t qutr_mask = (0xffff >> (TriggerProbes - TriggerProbes/4));
const uint16_t half_mask = (0xffff >> (TriggerProbes - TriggerProbes/2));
int i;
for (i = TriggerProbes - 1; i >= 0 ; i--) {
for (i = msc; i >= lsc ; i--) {
mask = (mask << 1);
mask += ((trigger->trigger0[stage][i] == 'X') | (trigger->trigger0[stage][i] == 'C'));
}
if (qutr_mode)
mask = ((mask & qutr_mask) << (TriggerProbes/4*3)) +
((mask & qutr_mask) << (TriggerProbes/4*2)) +
((mask & qutr_mask) << (TriggerProbes/4*1)) +
((mask & qutr_mask) << (TriggerProbes/4*0));
else if (half_mode)
mask = ((mask & half_mask) << (TriggerProbes/2*1)) +
((mask & half_mask) << (TriggerProbes/2*0));
return mask;
}
SR_PRIV uint64_t ds_trigger_get_mask1(uint16_t stage)
SR_PRIV uint16_t ds_trigger_get_mask1(uint16_t stage, uint16_t msc, uint16_t lsc, gboolean qutr_mode, gboolean half_mode)
{
assert(stage <= TriggerStages);
assert(lsc <= msc);
assert(msc < MaxTriggerProbes);
uint64_t mask = 0;
uint16_t mask = 0;
const uint16_t qutr_mask = (0xffff >> (TriggerProbes - TriggerProbes/4));
const uint16_t half_mask = (0xffff >> (TriggerProbes - TriggerProbes/2));
int i;
for (i = TriggerProbes - 1; i >= 0 ; i--) {
for (i = msc; i >= lsc ; i--) {
mask = (mask << 1);
mask += ((trigger->trigger1[stage][i] == 'X') | (trigger->trigger1[stage][i] == 'C'));
}
if (qutr_mode)
mask = ((mask & qutr_mask) << (TriggerProbes/4*3)) +
((mask & qutr_mask) << (TriggerProbes/4*2)) +
((mask & qutr_mask) << (TriggerProbes/4*1)) +
((mask & qutr_mask) << (TriggerProbes/4*0));
else if (half_mode)
mask = ((mask & half_mask) << (TriggerProbes/2*1)) +
((mask & half_mask) << (TriggerProbes/2*0));
return mask;
}
SR_PRIV uint64_t ds_trigger_get_value0(uint16_t stage)
SR_PRIV uint16_t ds_trigger_get_value0(uint16_t stage, uint16_t msc, uint16_t lsc, gboolean qutr_mode, gboolean half_mode)
{
assert(stage <= TriggerStages);
assert(lsc <= msc);
assert(msc < MaxTriggerProbes);
uint64_t value = 0;
uint16_t value = 0;
const uint16_t qutr_mask = (0xffff >> (TriggerProbes - TriggerProbes/4));
const uint16_t half_mask = (0xffff >> (TriggerProbes - TriggerProbes/2));
int i;
for (i = TriggerProbes - 1; i >= 0 ; i--) {
for (i = msc; i >= lsc ; i--) {
value = (value << 1);
value += ((trigger->trigger0[stage][i] == '1') | (trigger->trigger0[stage][i] == 'R'));
}
if (qutr_mode)
value = ((value & qutr_mask) << (TriggerProbes/4*3)) +
((value & qutr_mask) << (TriggerProbes/4*2)) +
((value & qutr_mask) << (TriggerProbes/4*1)) +
((value & qutr_mask) << (TriggerProbes/4*0));
else if (half_mode)
value = ((value & half_mask) << (TriggerProbes/2*1)) +
((value & half_mask) << (TriggerProbes/2*0));
return value;
}
SR_PRIV uint64_t ds_trigger_get_value1(uint16_t stage)
SR_PRIV uint16_t ds_trigger_get_value1(uint16_t stage, uint16_t msc, uint16_t lsc, gboolean qutr_mode, gboolean half_mode)
{
assert(stage <= TriggerStages);
assert(lsc <= msc);
assert(msc < MaxTriggerProbes);
uint64_t value = 0;
uint16_t value = 0;
const uint16_t qutr_mask = (0xffff >> (TriggerProbes - TriggerProbes/4));
const uint16_t half_mask = (0xffff >> (TriggerProbes - TriggerProbes/2));
int i;
for (i = TriggerProbes - 1; i >= 0 ; i--) {
for (i = msc; i >= lsc ; i--) {
value = (value << 1);
value += ((trigger->trigger1[stage][i] == '1') | (trigger->trigger1[stage][i] == 'R'));
}
if (qutr_mode)
value = ((value & qutr_mask) << (TriggerProbes/4*3)) +
((value & qutr_mask) << (TriggerProbes/4*2)) +
((value & qutr_mask) << (TriggerProbes/4*1)) +
((value & qutr_mask) << (TriggerProbes/4*0));
else if (half_mode)
value = ((value & half_mask) << (TriggerProbes/2*1)) +
((value & half_mask) << (TriggerProbes/2*0));
return value;
}
SR_PRIV uint64_t ds_trigger_get_edge0(uint16_t stage)
SR_PRIV uint16_t ds_trigger_get_edge0(uint16_t stage, uint16_t msc, uint16_t lsc, gboolean qutr_mode, gboolean half_mode)
{
assert(stage <= TriggerStages);
assert(lsc <= msc);
assert(msc < MaxTriggerProbes);
uint64_t edge = 0;
uint16_t edge = 0;
const uint16_t qutr_mask = (0xffff >> (TriggerProbes - TriggerProbes/4));
const uint16_t half_mask = (0xffff >> (TriggerProbes - TriggerProbes/2));
int i;
for (i = TriggerProbes - 1; i >= 0 ; i--) {
for (i = msc; i >= lsc ; i--) {
edge = (edge << 1);
edge += ((trigger->trigger0[stage][i] == 'R') | (trigger->trigger0[stage][i] == 'F') |
(trigger->trigger0[stage][i] == 'C'));
}
if (qutr_mode)
edge = ((edge & qutr_mask) << (TriggerProbes/4*3)) +
((edge & qutr_mask) << (TriggerProbes/4*2)) +
((edge & qutr_mask) << (TriggerProbes/4*1)) +
((edge & qutr_mask) << (TriggerProbes/4*0));
else if (half_mode)
edge = ((edge & half_mask) << (TriggerProbes/2*1)) +
((edge & half_mask) << (TriggerProbes/2*0));
return edge;
}
SR_PRIV uint64_t ds_trigger_get_edge1(uint16_t stage)
SR_PRIV uint16_t ds_trigger_get_edge1(uint16_t stage, uint16_t msc, uint16_t lsc, gboolean qutr_mode, gboolean half_mode)
{
assert(stage <= TriggerStages);
assert(lsc <= msc);
assert(msc < MaxTriggerProbes);
uint64_t edge = 0;
uint16_t edge = 0;
const uint16_t qutr_mask = (0xffff >> (TriggerProbes - TriggerProbes/4));
const uint16_t half_mask = (0xffff >> (TriggerProbes - TriggerProbes/2));
int i;
for (i = TriggerProbes - 1; i >= 0 ; i--) {
for (i = msc; i >= lsc ; i--) {
edge = (edge << 1);
edge += ((trigger->trigger1[stage][i] == 'R') | (trigger->trigger1[stage][i] == 'F') |
(trigger->trigger1[stage][i] == 'C'));
}
if (qutr_mode)
edge = ((edge & qutr_mask) << (TriggerProbes/4*3)) +
((edge & qutr_mask) << (TriggerProbes/4*2)) +
((edge & qutr_mask) << (TriggerProbes/4*1)) +
((edge & qutr_mask) << (TriggerProbes/4*0));
else if (half_mode)
edge = ((edge & half_mask) << (TriggerProbes/2*1)) +
((edge & half_mask) << (TriggerProbes/2*0));
return edge;
}
......
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