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  1. 04 Aug, 2000 1 commit
  3. 24 Jun, 2000 1 commit
  5. 30 Mar, 2000 1 commit
    • geoffk's avatar
      * c-common.c (c_common_nodes_and_builtins): The first parameter to · 2d47cc32
      geoffk authored 
      __builtin_va_start and __builtin_va_copy is now either a 'va_list'
or a reference to a va_list.
* builtins.c (stabilize_va_list): Simplify now we don't have to
work around C array address decay.
* c-typeck.c (convert_for_assignment): Handle assignment to
a reference parameter by taking the address of the RHS.
* ginclude/stdarg.h (va_start): Don't take address of first parameter.
(va_copy): Likewise.
(__va_copy): Likewise.
* ginclude/varargs.h (va_start): Likewise.
(__va_copy): Likewise.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@32821 138bc75d-0d04-0410-961f-82ee72b054a4
      2d47cc32
  7. 15 Feb, 2000 1 commit
  9. 06 Feb, 2000 1 commit
  11. 13 Jan, 2000 1 commit
    • jason's avatar
      * configure.in (i?86-*-beos{pe,elf,}*): Recognize. · 397f1574
      jason authored 
              * i386/t-beos, i386/x-beos, i386/xm-beos.h: New files.
        * i386/beos-elf.h, i386/beos-pe.h: New files.

        * Makefile.in (CROSS_SYSTEM_HEADER_DIR): New.
        * cross-make (SYSTEM_HEADER_DIR): Define using
        CROSS_SYSTEM_HEADER_DIR.

        * gcc.c (LIBRARY_PATH_ENV): Provide default.
        (process_command): Use it.
        (main): Likewise.  Kill trailing = from env vars.
        (build_search_list): Put it back.
        * collect2.c (main): Use LIBRARY_PATH_ENV.

        * configure.in (GCC_NEED_DECLARATIONS): Add environ.
        * toplev.c: Use NEED_DECLARATION_ENVIRON.

        * tm.texi (Frame Layout): Document SMALL_STACK.
        * c-common.c (c_common_nodes_and_builtins): Check it.

        * system.h: Undef alloca after including glibc's <stdlib.h>,
        if USE_C_ALLOCA is defined.

        * gcc.c (set_input): New fn.
        (main): After all input files are compiled, reset the input file
        info to the first.

        * aclocal.m4 (rindex, index): If already defined, don't attempt
        to redefine.

        * ginclude/varargs.h: (__va_list__): Define ifndef.
        * ginclude/stdarg.h: Likewise.

        * ginclude/stddef.h (__WCHAR_TYPE__) [BEOS]: Use int
        instead of unsigned char.

        * hash.h (true, false, boolean): Undef before enum.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@31366 138bc75d-0d04-0410-961f-82ee72b054a4
      397f1574
  13. 04 Jan, 2000 1 commit
  15. 19 Dec, 1999 1 commit
  17. 14 Dec, 1999 1 commit
    • rth's avatar
      * cppp.c (main): Set trigraphs and __STRICT_ANSI__ as · dd48bf24
      rth authored 
              appropriate for -lang-c89 and -std=*.
        * cppinit.c (cpp_handle_option): Likewise.
        (new_pending_define): New, split out from cpp_handle_option.
        * gcc.c (default_compilers): Don't define __STRICT_ANSI__
        or enable trigraphs for -ansi/-std=*.

        * ginclude/stdarg.h (__va_copy): New.
        (va_copy): Don't define for C89.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@30921 138bc75d-0d04-0410-961f-82ee72b054a4
      dd48bf24
  19. 15 Oct, 1999 1 commit
  21. 23 Sep, 1999 1 commit
  23. 15 Sep, 1999 1 commit
  25. 14 Sep, 1999 1 commit
  27. 29 Aug, 1999 1 commit
  29. 28 Jul, 1999 1 commit
  31. 21 Jul, 1999 1 commit
    • rth's avatar
      * rs6000.h (struct rs6000_args): Add sysv_gregno. · 036c1d46
      rth authored 
              * rs6000.c (init_cumulative_args): Init sysv_gregno.
        (function_arg_boundary): Align DFmode.
        (function_arg_advance): Restructure for ABI_V4; use sysv_gregno
        to get fp reg and stack overflow correct.
        (function_arg): Likewise.
        (function_arg_pass_by_reference): True for TFmode for ABI_V4.
        (setup_incoming_varargs): Restructure for ABI_V4; use
        function_arg_advance to skip final named argument.
        (expand_builtin_saveregs): Properly unskip the last integer arg
        when doing varargs.  Adjust overflow location calculation.

        * ginclude/va-ppc.h (struct __va_list_tag): Make gpr and fpr
        explicitly unsigned.
        (__VA_FP_REGSAVE): Use new OFS argument instead of AP->fpr directly.
        (__VA_GP_REGSAVE): Similarly.
        (__va_longlong_p): Delete.
        (__va_arg_type_violation): New declaration.
        (va_arg): Restructure.  Flag promotion errors.  Align double.
        TFmode passed by reference.

        * rs6000.md (movdi_32+1): Use GEN_INT after arithmetic
        in the HOST_BITS_PER_WIDE_INT > 32 case.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@28199 138bc75d-0d04-0410-961f-82ee72b054a4
      036c1d46
  33. 07 Jul, 1999 1 commit
    • law's avatar
      X · 90281314
      law authored 
              * ginclude/varargs.h (__builtin_va_alist_t): New typedef.
        (va_dcl): Use __builtin_va_alist_t.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@27971 138bc75d-0d04-0410-961f-82ee72b054a4
      90281314
  35. 02 Jul, 1999 1 commit
  37. 08 May, 1999 1 commit
  39. 30 Apr, 1999 1 commit
  41. 25 Feb, 1999 1 commit
    • amylaar's avatar
      * sh.h (PASS_IN_REG_P): For TARGET_HITACHI, don't pass structures · 8b823204
      amylaar authored 
      	in registers.
	* expr.h (PRETEND_OUTGOING_VARARGS_NAMED): Provide default definition.
	* function.c (assign_parms): Honour PRETEND_OUTGOING_VARARGS_NAMED.
	* calls.c (expand_call): Likewise.
	* sh.c (sh_expand_prologue): For TARGET_HITACHI, don't push varargs /
	stdarg arguments.
	* sh.h (CPP_SPEC): Add -D__HITACHI__ for -mhitachi.
	(FUNCTION_ARG):  For TARGET_HITACHI, don't pass unnamed
	arguments in registers.
	(PRETEND_OUTGOING_VARARGS_NAMED): Define.
	* va-sh.h (entire file): If __HITACHI__ is defined, use sh[123]
	flavour varargs.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@25440 138bc75d-0d04-0410-961f-82ee72b054a4
      8b823204
  43. 16 Dec, 1998 1 commit
  45. 23 Nov, 1998 1 commit
    • amylaar's avatar
      Add SH4 support: · 1b61190c
      amylaar authored 
      	* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
	(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
	* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
	(fp_reg_names, assembler_dialect): New variables.
	(print_operand_address): Handle SUBREGs.
	(print_operand): Added 'o' case.
	Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
	Name of FP registers depends on mode.
	(expand_block_move): Emit different code for SH4 hardware.
	(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
	(from_compare): Likewise.
	(add_constant): New argument last_value.  Changed all callers.
	(find_barrier): Don't try HImode load for FPUL_REG.
	(machine_dependent_reorg): Likewise.
	(sfunc_uses_reg): A CLOBBER cannot be the address register use.
	(gen_far_branch): Emit a barrier after the new jump.
	(barrier_align): Don't trust instruction lengths before
	fixing up pcloads.
	(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
	Use auto-inc addressing for fp registers if doubles need to
	be loaded in two steps.
	Set sh_flag_remove_dead_before_cse.
	(push): Support for TARGET_FMOVD.  Use gen_push_fpul for fpul.
	(pop): Support for TARGET_FMOVD.  Use gen_pop_fpul for fpul.
	(calc_live_regs): Support for TARGET_FMOVD.  Don't save FPSCR.
	Support for FIRST_XD_REG .. LAST_XD_REG.
	(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
	(sh_expand_epilogue): Likewise.
	(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
	(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
	(arith_reg_operand): FPUL_REG is OK for SH4.
	(fp_arith_reg_operand, fp_extended_operand) New functions.
	(tertiary_reload_operand, fpscr_operand): Likewise.
	(commutative_float_operator, noncommutative_float_operator): Likewise.
	(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
	(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
	(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
	(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
	* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
	(CONDITIONAL_REGISTER_USAGE): Likewise.
	(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
	(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
	(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
	(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
	(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
	to -1 and sh_flag_remove_dead_before_cse to 1.
	(ASSEMBLER_DIALECT): Define to assembler_dialect.
	(assembler_dialect, fp_reg_names): Declare.
	(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
	Hide names of registers that are not accessible.
	(CACHE_LOG): Take TARGET_CACHE32 into account.
	(LOOP_ALIGN): Take TARGET_HARWARD into account.
	(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
	(FIRST_PSEUDO_REGISTER: Now 49.
	(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
	(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
	(HARD_REGNO_MODE_OK): Update.
	(enum reg_class): Add DF_REGS and FPSCR_REGS.
	(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
	(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
	(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
	(NPARM_REGS): Eight floating point parameter registers on SH4.
	(BASE_RETURN_VALUE_REG): SH4 also passes double values
	in floating point registers.
	(GET_SH_ARG_CLASS) Likewise.
	Complex float types are also returned in float registers.
	(BASE_ARG_REG): Complex float types are also passes in float registers.
	(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
	(LIBCALL_VALUE): Remove trailing semicolon.
	(ROUND_REG): Round when double precision value is passed in floating
	point register(s).
	(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
	passed on the stack.
	(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
	(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
	(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
	(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
	(MODE_DISP_OK_8): Not for SH4 DFmode.
	(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
	Allow indexed addressing for PSImode after reload.
	(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
	(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
	Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
	(DOUBLE_TYPE_SIZE): 64 for SH4.
	(RTX_COSTS): Add PLUS case.
	Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
	(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
	MAC_REGS, PR_REGS, DF_REGS.
	(REGISTER_NAMES): Use fp_reg_names.
	(enum processor_type): Add PROCESSOR_SH4.
	(sh_flag_remove_dead_before_cse): Declare.
	(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
	(PREDICATE_CODES): Add binary_float_operator,
	commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
	fpscr_operand, noncommutative_float_operator.
	(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
	(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
	* sh.md (attribute cpu): Add value sh4.
	(attrbutes fmovd, issues): Define.
	(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
	(function units memory, int, mpy, fp): Make dependent on issue rate.
	(function units issue, single_issue, load_si, load): Define.
	(function units load_store, fdiv, gp_fpul): Define.
	(attribute hit_stack): Provide proper default.
	(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
	(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
	(udivsi3, divsi3): Emit special patterns for SH4 hardware,
	(mulsi3_call): Now uses match_operand for function address.
	(mulsi3): Also emit code for SH1 case.  Wrap result in REG_LIBCALL /
	REG_RETVAL notes.
	(push, pop, push_e, pop_e): Now define_expands.
	(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
	(movsi_ie): Added y/i alternative.
	(ic_invalidate_line_i, movdf_i4): New insns.
	(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
	(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
	(movdf): Add special code for SH4.
	(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
	(call_valuei, calli, call_value): Likewise.
	(movsf): Emit no-op move.
	(mov_nop, movsi_y): New insns.
	(blt, sge): generalize to handle DFmode.
	(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
	(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
	(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
	(fpu_switch0, fpu_switch1, movpsi): New expanders.
	(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
	(toggle_sz): New insn.
	(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
	(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
	(macsf3): Make use of fpscr visible.  Disable for SH4.
	(floatsisf2): Make use of fpscr visible.
	(floatsisf2_i4): New insn.
	(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
	(ieee_ccmpeqsf_t): Likewise.
	(fix_truncsfsi2): Emit different code for SH4.
	(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
	(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
	(negsf2, sqrtsf2, abssf2): Now expanders.
	(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
	(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
	(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
	(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
	(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
	(fix_truncdfsi2_i4_2+1): New splitters.
	(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
	(extendsfdf2, truncdfsf2): New expanders.
	(truncdfsf2_i4): New insn.
	* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
	(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
	* float-sh.h: When testing for __SH3E__, also test for
	__SH4_SINGLE_ONLY__ .
	* va-sh.h (__va_freg): Define to float.
	(__va_greg, __fa_freg, __gnuc_va_list, va_start):
        Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
        (__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
	(__PASS_AS_FLOAT): Use different definition for __SH4__ and
	 __SH4_SINGLE__.
	(TARGET_SH4_P): Define.
	(va_arg): Use it.
	* sh.md (movdf_k, movsf_i): Tweak the condition so that
	init_expr_once is satisfied about the existence of load / store insns.
	* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
        change m constraint in source operand to mr / mf .
	* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
	* (__VA_REEF): Define.
	(__va_arg_sh1): Use it.
	* va-sh.h (va_start, va_arg, va_copy): Add parenteses.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@23777 138bc75d-0d04-0410-961f-82ee72b054a4
      1b61190c
  47. 19 Nov, 1998 1 commit
  49. 19 Sep, 1998 2 commits
  51. 18 Sep, 1998 1 commit
    • dje's avatar
      * toplev.c (rest_of_compilation): Set bct_p on second call to · 879c6e0a
      dje authored 
              loop_optimize.
        * loop.c (loop_optimize, scan_loop, strength_reduce): New argument
        bct_p.
        (strength_reduce): Only call analyze_loop_iterations and
        insert_bct if bct_p set.
        (check_dbra_loop): Fix typo.
        (insert_bct): Use word_mode instead of SImode.
        (instrument_loop_bct): Likewise.  Do not delete iteration count
        condition code generation insn.  Initialize iteration count before
        loop start.
        * rtl.h (loop_optimize): Update prototype.
        * ginclude/va-ppc.h (va_arg): longlong types in overflow area are
        not doubleword aligned.
        * rs6000.c (optimization_options): New function.
        (secondary_reload_class): Only call true_regnum for PSEUDO_REGs.
        * rs6000.h (OPTIMIZATION_OPTIONS): Define.
        (REG_ALLOC_ORDER): Allocate highest numbered condition regsiters
        first; cr1 can be used for FP record condition insns.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@22471 138bc75d-0d04-0410-961f-82ee72b054a4
      879c6e0a
  53. 03 Sep, 1998 1 commit
  55. 01 Aug, 1998 1 commit
  57. 30 May, 1998 1 commit
  59. 28 Apr, 1998 1 commit
  61. 02 Apr, 1998 1 commit
  63. 01 Mar, 1998 1 commit
  65. 20 Feb, 1998 1 commit
  67. 16 Feb, 1998 1 commit
  69. 16 Dec, 1997 1 commit
  71. 12 Dec, 1997 1 commit
  73. 08 Dec, 1997 1 commit
  75. 06 Dec, 1997 1 commit
  77. 08 Nov, 1997 1 commit

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