- 10 Feb, 2017 1 commit
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Doug Gilbert authored
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- 28 Oct, 2016 1 commit
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Doug Gilbert authored
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Doug Gilbert authored
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- 15 Aug, 2016 14 commits
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Doug Gilbert authored
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Doug Gilbert authored
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Doug Gilbert authored
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Doug Gilbert authored
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Doug Gilbert authored
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Doug Gilbert authored
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Doug Gilbert authored
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Doug Gilbert authored
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Doug Gilbert authored
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Doug Gilbert authored
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Doug Gilbert authored
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Doug Gilbert authored
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Doug Gilbert authored
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Doug Gilbert authored
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- 23 Sep, 2014 1 commit
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meissner authored
* config/rs6000/rs6000.md (f32_vsx): New mode attributes to refine the constraints used on 32/64-bit floating point moves. (f32_av): Likewise. (f64_vsx): Likewise. (f64_dm): Likewise. (f64_av): Likewise. (BOOL_REGS_OUTPUT): Use wt constraint for TImode instead of wa. (BOOL_REGS_OP1): Likewise. (BOOL_REGS_OP2): Likewise. (BOOL_REGS_UNARY): Likewise. (mov<mode>_hardfloat, SFmode/SDmode): Tighten down constraints for 32/64-bit floating point moves. Do not use wa, instead use ww/ws for moves involving VSX registers. Do not use constraints that target VSX registers for decimal types. (mov<mode>_hardfloat32, DFmode/DDmode): Likewise. (mov<mode>_hardfloat64, DFmode/DDmode): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@215522 138bc75d-0d04-0410-961f-82ee72b054a4
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- 19 Sep, 2014 1 commit
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meissner authored
Back port from trunk: 2014-09-19 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/predicates.md (fusion_gpr_mem_load): Move testing for base_reg_operand to be common between LO_SUM and PLUS. (fusion_gpr_mem_combo): New predicate to match a fused address that combines the addis and memory offset address. * config/rs6000/rs6000-protos.h (fusion_gpr_load_p): Change calling signature. (emit_fusion_gpr_load): Likewise. * config/rs6000/rs6000.c (fusion_gpr_load_p): Change calling signature to pass each argument separately, rather than using an operands array. Rewrite the insns found by peephole2 to be a single insn, rather than hoping the insns will still be together when the peephole pass is done. Drop being called via a normal peephole. (emit_fusion_gpr_load): Change calling signature to be called from the fusion_gpr_load_<mode> insns with a combined memory address instead of the peephole pass passing the addis and offset separately. * config/rs6000/rs6000.md (UNSPEC_FUSION_GPR): New unspec for GPR fusion. (power8 fusion peephole): Drop support for doing power8 via a normal peephole that was created by the peephole2 pass. (power8 fusion peephole2): Create a new insn with the fused address, so that the fused operation is kept together after register allocation is done. (fusion_gpr_load_<mode>): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@215405 138bc75d-0d04-0410-961f-82ee72b054a4
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- 22 Aug, 2014 1 commit
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meissner authored
Backport fro mainline 2014-08-22 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/62195 * doc/md.texi (Machine Constraints): Update PowerPC wi constraint documentation to state it is only for VSX operations. * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Make wi constraint only active if VSX. * config/rs6000/rs6000.md (lfiwax): Use wj constraint instead of wi cosntraint for ISA 2.07 lxsiwax/lxsiwzx instructions. (lfiwzx): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@214336 138bc75d-0d04-0410-961f-82ee72b054a4
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- 12 Aug, 2014 1 commit
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meissner authored
Backport patch from mainline 2014-08-11 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/constraints.md (wh constraint): New constraint, for FP registers if direct move is available. (wi constraint): New constraint, for VSX/FP registers that can handle 64-bit integers. (wj constraint): New constraint for VSX/FP registers that can handle 64-bit integers for direct moves. (wk constraint): New constraint for VSX/FP registers that can handle 64-bit doubles for direct moves. (wy constraint): Make documentation match implementation. * config/rs6000/rs6000.c (struct rs6000_reg_addr): Add scalar_in_vmx_p field to simplify tests of whether SFmode or DFmode can go in the Altivec registers. (rs6000_hard_regno_mode_ok): Use scalar_in_vmx_p field. (rs6000_setup_reg_addr_masks): Likewise. (rs6000_debug_print_mode): Add debug support for scalar_in_vmx_p field, and wh/wi/wj/wk constraints. (rs6000_init_hard_regno_mode_ok): Setup scalar_in_vmx_p field, and the wh/wi/wj/wk constraints. (rs6000_preferred_reload_class): If SFmode/DFmode can go in the upper registers, prefer VSX registers unless the operation is a memory operation with REG+OFFSET addressing. * config/rs6000/vsx.md (VSr mode attribute): Add support for DImode. Change SFmode to use ww constraint instead of d to allow SF registers in the upper registers. (VSr2): Likewise. (VSr3): Likewise. (VSr5): Fix thinko in comment. (VSa): New mode attribute that is an alternative to wa, that returns the VSX register class that a mode can go in, but may not be the preferred register class. (VS_64dm): New mode attribute for appropriate register classes for referencing 64-bit elements of vectors for direct moves and normal moves. (VS_64reg): Likewise. (vsx_mov<mode>): Change wa constraint to <VSa> to limit the register allocator to only registers the data type can handle. (vsx_le_perm_load_<mode>): Likewise. (vsx_le_perm_store_<mode>): Likewise. (vsx_xxpermdi2_le_<mode>): Likewise. (vsx_xxpermdi4_le_<mode>): Likewise. (vsx_lxvd2x2_le_<mode>): Likewise. (vsx_lxvd2x4_le_<mode>): Likewise. (vsx_stxvd2x2_le_<mode>): Likewise. (vsx_add<mode>3): Likewise. (vsx_sub<mode>3): Likewise. (vsx_mul<mode>3): Likewise. (vsx_div<mode>3): Likewise. (vsx_tdiv<mode>3_internal): Likewise. (vsx_fre<mode>2): Likewise. (vsx_neg<mode>2): Likewise. (vsx_abs<mode>2): Likewise. (vsx_nabs<mode>2): Likewise. (vsx_smax<mode>3): Likewise. (vsx_smin<mode>3): Likewise. (vsx_sqrt<mode>2): Likewise. (vsx_rsqrte<mode>2): Likewise. (vsx_tsqrt<mode>2_internal): Likewise. (vsx_fms<mode>4): Likewise. (vsx_nfma<mode>4): Likewise. (vsx_eq<mode>): Likewise. (vsx_gt<mode>): Likewise. (vsx_ge<mode>): Likewise. (vsx_eq<mode>_p): Likewise. (vsx_gt<mode>_p): Likewise. (vsx_ge<mode>_p): Likewise. (vsx_xxsel<mode>): Likewise. (vsx_xxsel<mode>_uns): Likewise. (vsx_copysign<mode>3): Likewise. (vsx_float<VSi><mode>2): Likewise. (vsx_floatuns<VSi><mode>2): Likewise. (vsx_fix_trunc<mode><VSi>2): Likewise. (vsx_fixuns_trunc<mode><VSi>2): Likewise. (vsx_x<VSv>r<VSs>i): Likewise. (vsx_x<VSv>r<VSs>ic): Likewise. (vsx_btrunc<mode>2): Likewise. (vsx_b2trunc<mode>2): Likewise. (vsx_floor<mode>2): Likewise. (vsx_ceil<mode>2): Likewise. (vsx_<VS_spdp_insn>): Likewise. (vsx_xscvspdp): Likewise. (vsx_xvcvspuxds): Likewise. (vsx_float_fix_<mode>2): Likewise. (vsx_set_<mode>): Likewise. (vsx_extract_<mode>_internal1): Likewise. (vsx_extract_<mode>_internal2): Likewise. (vsx_extract_<mode>_load): Likewise. (vsx_extract_<mode>_store): Likewise. (vsx_splat_<mode>): Likewise. (vsx_xxspltw_<mode>): Likewise. (vsx_xxspltw_<mode>_direct): Likewise. (vsx_xxmrghw_<mode>): Likewise. (vsx_xxmrglw_<mode>): Likewise. (vsx_xxsldwi_<mode>): Likewise. (vsx_xscvdpspn): Tighten constraints to only use register classes the types use. (vsx_xscvspdpn): Likewise. (vsx_xscvdpspn_scalar): Likewise. * config/rs6000/rs6000.h (enum rs6000_reg_class_enum): Add wh, wi, wj, and wk constraints. (GPR_REG_CLASS_P): New helper macro for register classes targeting general purpose registers. * config/rs6000/rs6000.md (f32_dm): Use wh constraint for SDmode direct moves. (zero_extendsidi2_lfiwz): Use wj constraint for direct move of DImode instead of wm. Use wk constraint for direct move of DFmode instead of wm. (extendsidi2_lfiwax): Likewise. (lfiwax): Likewise. (lfiwzx): Likewise. (movdi_internal64): Likewise. * doc/md.texi (PowerPC and IBM RS6000): Document wh, wi, wj, and wk constraints. Make the wy constraint documentation match them implementation. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@213871 138bc75d-0d04-0410-961f-82ee72b054a4
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- 09 Aug, 2014 1 commit
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carrot authored
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@213769 138bc75d-0d04-0410-961f-82ee72b054a4
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- 04 Aug, 2014 1 commit
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edmarwjr authored
[libgcc] 2014-08-04 Rohit <rohitarulraj@freescale.com> * config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Update based on change in SPE high register numbers and 3 HTM registers. [gcc] 2014-08-04 Rohit <rohitarulraj@freescale.com> * config/rs6000/rs6000.c (rs6000_reg_names) : Add SPE high register names. (alt_reg_names) : Likewise. (rs6000_dwarf_register_span) : For SPE high registers, replace dwarf register numbers with GCC hard register numbers. (rs6000_init_dwarf_reg_sizes_extra) : Likewise. (rs6000_dbx_register_number): For SPE high registers, return dwarf register number for the corresponding GCC hard register number. * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER) : Update based on 32 newly added GCC hard register numbers for SPE high registers. (DWARF_FRAME_REGISTERS) : Likewise. (DWARF_REG_TO_UNWIND_COLUMN) : Likewise. (DWARF_FRAME_REGNUM) : Likewise. (FIXED_REGISTERS) : Likewise. (CALL_USED_REGISTERS) : Likewise. (CALL_REALLY_USED_REGISTERS) : Likewise. (REG_ALLOC_ORDER) : Likewise. (enum reg_class) : Likewise. (REG_CLASS_NAMES) : Likewise. (REG_CLASS_CONTENTS) : Likewise. (SPE_HIGH_REGNO_P) : New macro to identify SPE high registers. [gcc/testsuite] 2014-08-04 Rohit <rohitarulraj@freescale.com> * gcc.target/powerpc/pr60102.c: New testcase. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@213597 138bc75d-0d04-0410-961f-82ee72b054a4
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- 13 Jun, 2014 1 commit
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bergner authored
Backport from mainline 2014-06-13 Peter Bergner <bergner@vnet.ibm.com> PR target/61415 * config/rs6000/rs6000-builtin.def (BU_MISC_1): Delete. (BU_MISC_2): Rename to ... (BU_LDBL128_2): ... this. * config/rs6000/rs6000.h (RS6000_BTM_LDBL128): New define. (RS6000_BTM_COMMON): Add RS6000_BTM_LDBL128. * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Handle RS6000_BTM_LDBL128. (rs6000_invalid_builtin): Add long double 128-bit builtin support. (rs6000_builtin_mask_names): Add RS6000_BTM_LDBL128. * config/rs6000/rs6000.md (unpacktf_0): Remove define)expand. (unpacktf_1): Likewise. * doc/extend.texi (__builtin_longdouble_dw0): Remove documentation. (__builtin_longdouble_dw1): Likewise. * doc/sourcebuild.texi (longdouble128): Document. gcc/testsuite/ Backport from mainline 2014-06-13 Peter Bergner <bergner@vnet.ibm.com> PR target/61415 * lib/target-supports.exp (check_effective_target_longdouble128): New. * gcc.target/powerpc/pack02.c: Use it. * gcc.target/powerpc/tfmode_off.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@211656 138bc75d-0d04-0410-961f-82ee72b054a4
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- 23 May, 2014 1 commit
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amodra authored
* config/rs6000/rs6000.c (mem_operand_gpr): Handle SImode. * config/rs6000/rs6000.md (extendsidi2_lfiwax, extendsidi2_nocell): Use "Y" constraint rather than "m". git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@210836 138bc75d-0d04-0410-961f-82ee72b054a4
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- 30 Apr, 2014 1 commit
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meissner authored
2014-04-30 Michael Meissner <meissner@linux.vnet.ibm.com> Back port from mainline 2014-04-24 Michael Meissner <meissner@linux.vnet.ibm.com> * doc/extend.texi (PowerPC Built-in Functions): Document new powerpc extended divide, bcd, pack/unpack 128-bit, builtin functions. (PowerPC AltiVec/VSX Built-in Functions): Likewise. * config/rs6000/predicates.md (const_0_to_3_operand): New predicate to match 0..3 integer constants. * config/rs6000/rs6000-builtin.def (BU_DFP_MISC_1): Add new macros to support adding miscellaneous builtin functions. (BU_DFP_MISC_2): Likewise. (BU_P7_MISC_1): Likewise. (BU_P7_MISC_2): Likewise. (BU_P8V_MISC_3): Likewise. (BU_MISC_1): Likewise. (BU_MISC_2): Likewise. (DIVWE): Add extended divide builtin functions. (DIVWEO): Likewise. (DIVWEU): Likewise. (DIVWEUO): Likewise. (DIVDE): Likewise. (DIVDEO): Likewise. (DIVDEU): Likewise. (DIVDEUO): Likewise. (DXEX): Add decimal floating-point builtin functions. (DXEXQ): Likewise. (DDEDPD): Likewise. (DDEDPDQ): Likewise. (DENBCD): Likewise. (DENBCDQ): Likewise. (DIEX): Likewise. (DIEXQ): Likewise. (DSCLI): Likewise. (DSCLIQ): Likewise. (DSCRI): Likewise. (DSCRIQ): Likewise. (CDTBCD): Add new BCD builtin functions. (CBCDTD): Likewise. (ADDG6S): Likewise. (BCDADD): Likewise. (BCDADD_LT): Likewise. (BCDADD_EQ): Likewise. (BCDADD_GT): Likewise. (BCDADD_OV): Likewise. (BCDSUB): Likewise. (BCDSUB_LT): Likewise. (BCDSUB_EQ): Likewise. (BCDSUB_GT): Likewise. (BCDSUB_OV): Likewise. (PACK_TD): Add new pack/unpack 128-bit type builtin functions. (UNPACK_TD): Likewise. (PACK_TF): Likewise. (UNPACK_TF): Likewise. (UNPACK_TF_0): Likewise. (UNPACK_TF_1): Likewise. (PACK_V1TI): Likewise. (UNPACK_V1TI): Likewise. * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add support for decimal floating point builtin functions. (rs6000_expand_ternop_builtin): Add checks for the new builtin functions that take constant arguments. (rs6000_invalid_builtin): Add decimal floating point builtin support. (rs6000_init_builtins): Setup long double, _Decimal64, and _Decimal128 types for new builtin functions. (builtin_function_type): Set the unsigned flags appropriately for the new builtin functions. (rs6000_opt_masks): Add support for decimal floating point builtin functions. * config/rs6000/rs6000.h (RS6000_BTM_DFP): Add support for decimal floating point builtin functions. (RS6000_BTM_COMMON): Likewise. (RS6000_BTI_long_double): Likewise. (RS6000_BTI_dfloat64): Likewise. (RS6000_BTI_dfloat128): Likewise. (long_double_type_internal_node): Likewise. (dfloat64_type_internal_node): Likewise. (dfloat128_type_internal_node): Likewise. * config/rs6000/altivec.h (UNSPEC_BCDADD): Add support for ISA 2.07 bcd arithmetic instructions. (UNSPEC_BCDSUB): Likewise. (UNSPEC_BCD_OVERFLOW): Likewise. (UNSPEC_BCD_ADD_SUB): Likewise. (bcd_add_sub): Likewise. (BCD_TEST): Likewise. (bcd<bcd_add_sub>): Likewise. (bcd<bcd_add_sub>_test): Likewise. (bcd<bcd_add_sub>_test2): Likewise. (bcd<bcd_add_sub>_<code>): Likewise. (peephole2 for combined bcd ops): Likewise. * config/rs6000/dfp.md (UNSPEC_DDEDPD): Add support for new decimal floating point builtin functions. (UNSPEC_DENBCD): Likewise. (UNSPEC_DXEX): Likewise. (UNSPEC_DIEX): Likewise. (UNSPEC_DSCLI): Likewise. (UNSPEC_DSCRI): Likewise. (D64_D128): Likewise. (dfp_suffix): Likewise. (dfp_ddedpd_<mode>): Likewise. (dfp_denbcd_<mode>): Likewise. (dfp_dxex_<mode>): Likewise. (dfp_diex_<mode>): Likewise. (dfp_dscli_<mode>): Likewise. (dfp_dscri_<mode>): Likewise. * config/rs6000/rs6000.md (UNSPEC_ADDG6S): Add support for new BCD builtin functions. (UNSPEC_CDTBCD): Likewise. (UNSPEC_CBCDTD): Likewise. (UNSPEC_DIVE): Add support for new extended divide builtin functions. (UNSPEC_DIVEO): Likewise. (UNSPEC_DIVEU): Likewise. (UNSPEC_DIVEUO): Likewise. (UNSPEC_UNPACK_128BIT): Add support for new builtin functions to pack/unpack 128-bit types. (UNSPEC_PACK_128BIT): Likewise. (idiv_ldiv): New mode attribute to set the 32/64-bit divide type. (udiv<mode>3): Use idiv_ldiv mode attribute. (div<mode>3): Likewise. (addg6s): Add new BCD builtin functions. (cdtbcd): Likewise. (cbcdtd): Likewise. (UNSPEC_DIV_EXTEND): Add support for new extended divide instructions. (div_extend): Likewise. (div<div_extend>_<mode>"): Likewise. (FP128_64): Add support for new builtin functions to pack/unpack 128-bit types. (unpack<mode>): Likewise. (unpacktf_0): Likewise. (unpacktf_1): Likewise. (unpack<mode>_dm): Likewise. (unpack<mode>_nodm): Likewise. (pack<mode>): Likewise. (unpackv1ti): Likewise. (packv1ti): Likewise. [gcc/testsuite] 2014-04-30 Michael Meissner <meissner@linux.vnet.ibm.com> Back port from mainline 2014-04-24 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/pack01.c: New test to test the new pack and unpack builtin functionss for 128-bit types. * gcc.target/powerpc/pack02.c: Likewise. * gcc.target/powerpc/pack03.c: Likewise. * gcc.target/powerpc/extend-divide-1.c: New test to test extended divide builtin functionss. * gcc.target/powerpc/extend-divide-2.c: Likewise. * gcc.target/powerpc/bcd-1.c: New test for the new BCD builtin functions. * gcc.target/powerpc/bcd-2.c: Likewise. * gcc.target/powerpc/bcd-3.c: Likewise. * gcc.target/powerpc/dfp-builtin-1.c: New test for the new DFP builtin functionss. * gcc.target/powerpc/dfp-builtin-2.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@209954 138bc75d-0d04-0410-961f-82ee72b054a4
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- 29 Apr, 2014 1 commit
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pthaugen authored
* gcc.target/powerpc/ti_math1.c: New. * gcc.target/powerpc/ti_math2.c: New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@209912 138bc75d-0d04-0410-961f-82ee72b054a4
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- 28 Apr, 2014 1 commit
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pthaugen authored
(loadsync_<mode>): Change mode. (load_quadpti, store_quadpti): New. (atomic_load<mode>, atomic_store<mode>): Add support for TI mode. * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@209876 138bc75d-0d04-0410-961f-82ee72b054a4
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- 22 Apr, 2014 1 commit
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meissner authored
2014-04-21 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/60735 * config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64 case): If mode is DDmode and TARGET_E500_DOUBLE allow move. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print some more debug information for E500 if -mdebug=reg. [gcc/testsuite] 2014-04-21 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/60735 * gcc.target/powerpc/pr60735.c: New test. Insure _Decimal64 does not cause errors if -mspe. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@209664 138bc75d-0d04-0410-961f-82ee72b054a4
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- 15 Apr, 2014 1 commit
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wschmidt authored
PR target/60839 Revert the following patch 2014-04-02 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/60735 * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have software floating point or no floating point registers, do not allow any type in the FPRs. Eliminate a test for SPE SIMD types in GPRs that occurs after we tested for GPRs that would never be true. * config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64): Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE, since the FMOVE64 type is DFmode/DDmode. If TARGET_E500_DOUBLE, specifically allow DDmode, since that does not use the SPE SIMD instructions. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@209426 138bc75d-0d04-0410-961f-82ee72b054a4
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- 09 Apr, 2014 1 commit
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dje authored
2014-04-08 Pat Haugen <pthaugen@us.ibm.com> * config/rs6000/sync.md (AINT mode_iterator): Move definition. (loadsync_<mode>): Change mode. (load_quadpti, store_quadpti): New. (atomic_load<mode>, atomic_store<mode>): Add support for TI mode. * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ. * config/rs6000/predicates.md (quad_memory_operand): !TARGET_SYNC_TI. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@209253 138bc75d-0d04-0410-961f-82ee72b054a4
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- 08 Apr, 2014 2 commits
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pthaugen authored
(loadsync_<mode>): Change mode. (load_quadpti, store_quadpti): New. (atomic_load<mode>, atomic_store<mode>): Add support for TI mode. * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ. * gcc.target/powerpc/atomic_load_store-p8.c: New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@209225 138bc75d-0d04-0410-961f-82ee72b054a4
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rsandifo authored
PR target/60763 * config/rs6000/vsx.md (vsx_xscvdpspn_scalar): Change input to DImode. * config/rs6000/rs6000.md (reload_vsx_from_gprsf): Update accordingly. Use gen_rtx_REG rather than simplify_gen_subreg for op0_di. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@209223 138bc75d-0d04-0410-961f-82ee72b054a4
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- 02 Apr, 2014 1 commit
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meissner authored
PR target/60735 * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have software floating point or no floating point registers, do not allow any type in the FPRs. Eliminate a test for SPE SIMD types in GPRs that occurs after we tested for GPRs that would never be true. * config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64): Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE, since the FMOVE64 type is DFmode/DDmode. If TARGET_E500_DOUBLE, specifically allow DDmode, since that does not use the SPE SIMD instructions. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@209025 138bc75d-0d04-0410-961f-82ee72b054a4
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- 13 Mar, 2014 1 commit
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meissner authored
2014-03-12 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/vector.md (VEC_L): Add V1TI mode to vector types. (VEC_M): Likewise. (VEC_N): Likewise. (VEC_R): Likewise. (VEC_base): Likewise. (mov<MODE>, VEC_M modes): If we are loading TImode into VSX registers, we need to swap double words in little endian mode. * config/rs6000/rs6000-modes.def (V1TImode): Add new vector mode to be a container mode for 128-bit integer operations added in ISA 2.07. Unlike TImode and PTImode, the preferred register set is the Altivec/VMX registers for the 128-bit operations. * config/rs6000/rs6000-protos.h (rs6000_move_128bit_ok_p): Add declarations. (rs6000_split_128bit_ok_p): Likewise. * config/rs6000/rs6000-builtin.def (BU_P8V_AV_3): Add new support macros for creating ISA 2.07 normal and overloaded builtin functions with 3 arguments. (BU_P8V_OVERLOAD_3): Likewise. (VPERM_1T): Add support for V1TImode in 128-bit vector operations for use as overloaded functions. (VPERM_1TI_UNS): Likewise. (VSEL_1TI): Likewise. (VSEL_1TI_UNS): Likewise. (ST_INTERNAL_1ti): Likewise. (LD_INTERNAL_1ti): Likewise. (XXSEL_1TI): Likewise. (XXSEL_1TI_UNS): Likewise. (VPERM_1TI): Likewise. (VPERM_1TI_UNS): Likewise. (XXPERMDI_1TI): Likewise. (SET_1TI): Likewise. (LXVD2X_V1TI): Likewise. (STXVD2X_V1TI): Likewise. (VEC_INIT_V1TI): Likewise. (VEC_SET_V1TI): Likewise. (VEC_EXT_V1TI): Likewise. (EQV_V1TI): Likewise. (NAND_V1TI): Likewise. (ORC_V1TI): Likewise. (VADDCUQ): Add support for 128-bit integer arithmetic instructions added in ISA 2.07. Add both normal 'altivec' builtins, and the overloaded builtin. (VADDUQM): Likewise. (VSUBCUQ): Likewise. (VADDEUQM): Likewise. (VADDECUQ): Likewise. (VSUBEUQM): Likewise. (VSUBECUQ): Likewise. * config/rs6000/rs6000-c.c (__int128_type): New static to hold __int128_t and __uint128_t types. (__uint128_type): Likewise. (altivec_categorize_keyword): Add support for vector __int128_t, vector __uint128_t, vector __int128, and vector unsigned __int128 as a container type for TImode operations that need to be done in VSX/Altivec registers. (rs6000_macro_to_expand): Likewise. (altivec_overloaded_builtins): Add ISA 2.07 overloaded functions to support 128-bit integer instructions vaddcuq, vadduqm, vaddecuq, vaddeuqm, vsubcuq, vsubuqm, vsubecuq, vsubeuqm. (altivec_resolve_overloaded_builtin): Add support for V1TImode. * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Add support for V1TImode, and set up preferences to use VSX/Altivec registers. Setup VSX reload handlers. (rs6000_debug_reg_global): Likewise. (rs6000_init_hard_regno_mode_ok): Likewise. (rs6000_preferred_simd_mode): Likewise. (vspltis_constant): Do not allow V1TImode as easy altivec constants. (easy_altivec_constant): Likewise. (output_vec_const_move): Likewise. (rs6000_expand_vector_set): Convert V1TImode set and extract to simple move. (rs6000_expand_vector_extract): Likewise. (reg_offset_addressing_ok_p): Setup V1TImode to use VSX reg+reg addressing. (rs6000_const_vec): Add support for V1TImode. (rs6000_emit_le_vsx_load): Swap double words when loading or storing TImode/V1TImode. (rs6000_emit_le_vsx_store): Likewise. (rs6000_emit_le_vsx_move): Likewise. (rs6000_emit_move): Add support for V1TImode. (altivec_expand_ld_builtin): Likewise. (altivec_expand_st_builtin): Likewise. (altivec_expand_vec_init_builtin): Likewise. (altivec_expand_builtin): Likewise. (rs6000_init_builtins): Add support for V1TImode type. Add support for ISA 2.07 128-bit integer builtins. Define type names for the VSX/Altivec vector types. (altivec_init_builtins): Add support for overloaded vector functions with V1TImode type. (rs6000_preferred_reload_class): Prefer Altivec registers for V1TImode. (rs6000_move_128bit_ok_p): Move 128-bit move/split validation to external function. (rs6000_split_128bit_ok_p): Likewise. (rs6000_handle_altivec_attribute): Create V1TImode from vector __int128_t and vector __uint128_t. * config/rs6000/vsx.md (VSX_L): Add V1TImode to vector iterators and mode attributes. (VSX_M): Likewise. (VSX_M2): Likewise. (VSm): Likewise. (VSs): Likewise. (VSr): Likewise. (VSv): Likewise. (VS_scalar): Likewise. (VS_double): Likewise. (vsx_set_v1ti): New builtin function to create V1TImode from TImode. * config/rs6000/rs6000.h (TARGET_VADDUQM): New macro to say whether we support the ISA 2.07 128-bit integer arithmetic instructions. (ALTIVEC_OR_VSX_VECTOR_MODE): Add V1TImode. (enum rs6000_builtin_type_index): Add fields to hold V1TImode and TImode types for use with the builtin functions. (V1TI_type_node): Likewise. (unsigned_V1TI_type_node): Likewise. (intTI_type_internal_node): Likewise. (uintTI_type_internal_node): Likewise. * config/rs6000/altivec.md (UNSPEC_VADDCUQ): New unspecs for ISA 2.07 128-bit builtin functions. (UNSPEC_VADDEUQM): Likewise. (UNSPEC_VADDECUQ): Likewise. (UNSPEC_VSUBCUQ): Likewise. (UNSPEC_VSUBEUQM): Likewise. (UNSPEC_VSUBECUQ): Likewise. (VM): Add V1TImode to vector mode iterators. (VM2): Likewise. (VI_unit): Likewise. (altivec_vadduqm): Add ISA 2.07 128-bit binary builtins. (altivec_vaddcuq): Likewise. (altivec_vsubuqm): Likewise. (altivec_vsubcuq): Likewise. (altivec_vaddeuqm): Likewise. (altivec_vaddecuq): Likewise. (altivec_vsubeuqm): Likewise. (altivec_vsubecuq): Likewise. * config/rs6000/rs6000.md (FMOVE128_GPR): Add V1TImode to vector mode iterators. (BOOL_128): Likewise. (BOOL_REGS_OUTPUT): Likewise. (BOOL_REGS_OP1): Likewise. (BOOL_REGS_OP2): Likewise. (BOOL_REGS_UNARY): Likewise. (BOOL_REGS_AND_CR0): Likewise. * config/rs6000/altivec.h (vec_vaddcuq): Add support for ISA 2.07 128-bit integer builtin support. (vec_vadduqm): Likewise. (vec_vaddecuq): Likewise. (vec_vaddeuqm): Likewise. (vec_vsubecuq): Likewise. (vec_vsubeuqm): Likewise. (vec_vsubcuq): Likewise. (vec_vsubuqm): Likewise. * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): Document vec_vaddcuq, vec_vadduqm, vec_vaddecuq, vec_vaddeuqm, vec_subecuq, vec_subeuqm, vec_vsubcuq, vec_vsubeqm builtins adding 128-bit integer add/subtract to ISA 2.07. [gcc/testsuite] 2014-03-12 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/p8vector-int128-1.c: New test to test ISA 2.07 128-bit arithmetic. * gcc.target/powerpc/p8vector-int128-2.c: Likewise. * gcc.target/powerpc/timode_off.c: Restrict cpu type to power5, due to when TImode is allowed in VSX registers, the allowable address modes for TImode is just a single indirect address in order for the value to be loaded and store in either GPR or VSX registers. This affects the generated code, and it would cause this test to fail, when such an option is used. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208522 138bc75d-0d04-0410-961f-82ee72b054a4
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- 19 Feb, 2014 1 commit
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meissner authored
PR target/60203 * config/rs6000/rs6000.md (mov<mode>_64bit, TF/TDmode moves): Split 64-bit moves into 2 patterns. Do not allow the use of direct move for TDmode in little endian, since the decimal value has little endian bytes within a word, but the 64-bit pieces are ordered in a big endian fashion, and normal subreg's of TDmode are not allowed. (mov<mode>_64bit_dm): Likewise. (movtd_64bit_nodm): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@207868 138bc75d-0d04-0410-961f-82ee72b054a4
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- 16 Feb, 2014 1 commit
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meissner authored
2014-02-15 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/60203 * config/rs6000/rs6000.md (rreg): Add TFmode, TDmode constraints. (mov<mode>_internal, TFmode/TDmode): Split TFmode/TDmode moves into 64-bit and 32-bit moves. On 64-bit moves, add support for using direct move instructions on ISA 2.07. Also adjust instruction length for 64-bit. (mov<mode>_64bit, TFmode/TDmode): Likewise. (mov<mode>_32bit, TFmode/TDmode): Likewise. [gcc/testsuite] 2014-02-15 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/60203 * gcc.target/powerpc/pr60203.c: New testsuite. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@207808 138bc75d-0d04-0410-961f-82ee72b054a4
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- 11 Feb, 2014 1 commit
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meissner authored
2014-02-11 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/60137 * config/rs6000/rs6000.md (128-bit GPR splitter): Add a splitter for VSX/Altivec vectors that land in GPR registers. [gcc/testsuite] 2014-02-11 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/60137 * gcc.target/powerpc/pr60137.c: New file. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@207699 138bc75d-0d04-0410-961f-82ee72b054a4
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- 16 Jan, 2014 1 commit
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meissner authored
PR target/59844 * config/rs6000/rs6000.md (reload_vsx_from_gprsf): Add little endian support, remove tests for WORDS_BIG_ENDIAN. (p8_mfvsrd_3_<mode>): Likewise. (reload_gpr_from_vsx<mode>): Likewise. (reload_gpr_from_vsxsf): Likewise. (p8_mfvsrd_4_disf): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@206668 138bc75d-0d04-0410-961f-82ee72b054a4
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- 11 Jan, 2014 1 commit
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dje authored
* config/rs6000/rs6000.h (SWITCHABLE_TARGET): Define. * config/rs6000/rs6000.c: Include target-globals.h. (rs6000_set_current_function): Instead of doing target_reinit unconditionally, use save_target_globals_default_opts and restore_target_globals. * config/rs6000/rs6000-builtin.def (mffs, mtfsf): Add builtins for FPSCR. * config/rs6000/rs6000.c (rs6000_expand_mtfsf_builtin): New. (rs6000_expand_builtin): Handle mffs and mtfsf. (rs6000_init_builtins): Define mffs and mtfsf. * config/rs6000/rs6000.md (UNSPECV_MFFS, UNSPECV_MTFSF): New. (rs6000_mffs): New pattern. (rs6000_mtfsf): New pattern. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@206554 138bc75d-0d04-0410-961f-82ee72b054a4
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