GitLab

	* config/arm/thumb2.md (peephole2 to convert zero_extract/compare
	of lowest bits to lshift/compare): Add a missing line.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161930 138bc75d-0d04-0410-961f-82ee72b054a4

        * config/arm/thumb2.md (peephole2 to convert zero_extract/compare
        of lowest bits to lshift/compare): New.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161929 138bc75d-0d04-0410-961f-82ee72b054a4

	* doc/tm.texi: Update.
	* doc/tm.texi.in (SDB and DWARF) <TARGET_WANT_DEBUG_PUB_SECTIONS>:
	Add @hook.
	* target.def (want_debug_pub_sections): New hook.
	* config/darwin.h (TARGET_WANT_DEBUG_PUB_SECTIONS): Define.
	* dwarf2out.c (add_pubname_string): Check
	targetm.want_debug_pub_sections.
	(add_pubname): Likewise.
	(add_pubtype): Likewise.
gcc/testsuite
	* g++.dg/debug/dwarf2/pubnames-1.C: Make darwin-specific.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161924 138bc75d-0d04-0410-961f-82ee72b054a4

2010-07-07  H.J. Lu  <hongjiu.lu@intel.com>

	PR target/44850
	* config/i386/i386.c (ix86_function_ms_hook_prologue): Revert
	revision 161876.
	(ix86_expand_prologue): Likewise.
	(ix86_handle_fndecl_attribute): Likewise.
	(ix86_asm_declare_function_name): Likewise.
	* config/i386/i386.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
	* config/i386/cygming.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
	(SUBTARGET_ASM_DECLARE_FUNCTION_NAME): Likewise.
	* config/i386/i386-protos.h (ix86_asm_declare_function_name):
	Likewise.
	* doc/extend.texi: Likewise.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161911 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/

2010-07-07  H.J. Lu  <hongjiu.lu@intel.com>

	PR target/44844
	* config/i386/i386.md (rdrand<mode>): Changed to expand to
	retry if the carry flag isn't valid.
	(rdrand<mode>_1): New.

gcc/testsuite/

2010-07-07  H.J. Lu  <hongjiu.lu@intel.com>

	PR target/44844
	* gcc.target/i386/rdrand-1.c: Scan "jnc".
	* gcc.target/i386/rdrand-2.c: Likewise.
	* gcc.target/i386/rdrand-3.c: Likewise.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161910 138bc75d-0d04-0410-961f-82ee72b054a4

	* config/arm/arm.md (arith_shiftsi): Allow stack pointer in operand 2.
	* config/arm/thumb2.md (thumb2_arith_shiftsi): Likewise.

testsuite/
	PR rtl-optimization/44787
	* gcc.c-torture/compile/pr44788.c: New test.
	* gcc.target/arm/pr44788.c: New test.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161893 138bc75d-0d04-0410-961f-82ee72b054a4

        * config/i386/i386.c (ix86_function_ms_hook_prologue): Enable x64
        support.
        (ix86_expand_prologue): Likewise.
        (ix86_handle_fndecl_attribute): Likewise.
        (ix86_asm_declare_function_name): New function for
        ASM_DECLARE_FUNCTION_NAME.
        * config/i386/i386.h (ASM_DECLARE_FUNCTION_NAME): New macro.
        * config/i386/cygming.h (ASM_DECLARE_FUNCTION_NAME): Removed.
        (SUBTARGET_ASM_DECLARE_FUNCTION_NAME): New macro.
        * config/i386/i386-protos.h (ix86_asm_declare_function_name): New.
        * doc/extend.texi: Adjust documentation about ms_hook_prologue
        attribute.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161876 138bc75d-0d04-0410-961f-82ee72b054a4

	* config/i386/i386.md (immediate_operand): New mode attribute.
	
	(pro_epilogue_adjust_stack_<mode>_1): Macroize insn from
	pro_epilogue_adjust_stack  and pro_epilogue_adjust_stack_rex64
	using P mode iterator.
	(pro_epilogue_adjust_stack_di_2): Rename from
	pro_epilogue_adjust_stack_rex64_2.

	* config/i386/i386.c (pro_epilogue_adjust_stack): Update for rename.

2010-07-06  Uros Bizjak  <ubizjak@gmail.com>

	* config/i386/i386.md (insv): Call gen_movdi_insv1 or gen_movsi_insv1
	through gen_mov_insv_1 function pointer.
	(fmod<mode>3): Call gen_truncxf<mode>2_i387_noop_unspec or
	gen_truncxf<mode>2 through gen_truncxf function pointer.
	(remainder<mode>3): Ditto.
	(cmpstrnsi): Rename cmp_insn function pointer to gen_cmp.
	(allocate_stack): Call gen_allocate_stack_worker_64 or
	gen_allocate_stack_worker_32 through gen_allocate_stack_worker
	function pointer.
	(probe_stack): Call gen_iordi3 or gen_iorsi3 through gen_ior3
	function pointer.

2010-07-06  Uros Bizjak  <ubizjak@gmail.com>

	* config/i386/i386.md (*add<mode>3_cconly_overflow): Use <g>
	operand constraint instead of <r><i>m.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161870 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/

2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>

	AVX Programming Reference (June, 2010)
	* config/i386/cpuid.h (bit_F16C): New.
	(bit_RDRND): Likewise.
	(bit_FSGSBASE): Likewise.

	* config/i386/i386-builtin-types.def: Add
	"DEF_FUNCTION_TYPE (UINT16)", function types for
	float16 <-> float conversions and
	"DEF_FUNCTION_TYPE (VOID, UINT64)".

	* config/i386/i386-c.c (ix86_target_macros_internal): Support
	OPTION_MASK_ISA_FSGSBASE, OPTION_MASK_ISA_RDRND and
	OPTION_MASK_ISA_F16C.

	* config/i386/i386.c (OPTION_MASK_ISA_FSGSBASE_SET): New.
	(OPTION_MASK_ISA_RDRND_SET): Likewise.
	(OPTION_MASK_ISA_F16C_SET): Likewise.
	(OPTION_MASK_ISA_FSGSBASE_UNSET): Likewise.
	(OPTION_MASK_ISA_RDRND_UNSET): Likewise.
	(OPTION_MASK_ISA_F16C_UNSET): Likewise.
	(OPTION_MASK_ISA_AVX_UNSET): Add OPTION_MASK_ISA_F16C_UNSET.
	(ix86_handle_option): Handle OPT_mfsgsbase, OPT_mrdrnd and
	OPT_mf16c.
	(ix86_target_string): Support -mfsgsbase, -mrdrnd and -mf16c.
	(pta_flags): Add PTA_FSGSBASE, PTA_RDRND and PTA_F16C.
	(override_options): Handle them.
	(ix86_valid_target_attribute_inner_p): Handle fsgsbase, rdrnd
	and f16c.
	(ix86_builtins): Add IX86_BUILTIN_RDFSBASE32,
	IX86_BUILTIN_RDFSBASE64, IX86_BUILTIN_RDGSBASE32,
	IX86_BUILTIN_RDGSBASE64, IX86_BUILTIN_WRFSBASE32,
	IX86_BUILTIN_WRFSBASE64, IX86_BUILTIN_WRGSBASE32,
	IX86_BUILTIN_WRGSBASE64, IX86_BUILTIN_RDRAND16,
	IX86_BUILTIN_RDRAND32, IX86_BUILTIN_RDRAND64,
	IX86_BUILTIN_CVTPH2PS, IX86_BUILTIN_CVTPH2PS256,
	IX86_BUILTIN_CVTPS2PH and IX86_BUILTIN_CVTPS2PH256.
	(bdesc_args): Likewise.
	(ix86_expand_args_builtin): Handle V8SF_FTYPE_V8HI,
	V4SF_FTYPE_V8HI, V8HI_FTYPE_V8SF_INT and V8HI_FTYPE_V4SF_INT.
	(ix86_expand_special_args_builtin): Handle VOID_FTYPE_UINT64,
	VOID_FTYPE_UNSIGNED, UNSIGNED_FTYPE_VOID and UINT16_FTYPE_VOID.
	Handle non-memory store.

	* config/i386/i386.h (TARGET_FSGSBASE): New.
	(TARGET_RDRND): Likewise.
	(TARGET_F12C): Likewise.

	* config/i386/i386.md (UNSPEC_VCVTPH2PS): New.
	(UNSPEC_VCVTPS2PH): Likewise.
	(UNSPECV_RDFSBASE): Likewise.
	(UNSPECV_RDGSBASE): Likewise.
	(UNSPECV_WRFSBASE): Likewise.
	(UNSPECV_WRGSBASE): Likewise.
	(UNSPECV_RDRAND): Likewise.
	(rdfsbase<mode>): Likewise.
	(rdgsbase<mode>): Likewise.
	(wrfsbase<mode>): Likewise.
	(wrgsbase<mode>): Likewise.
	(rdrand<mode>): Likewise.

	* config/i386/i386.opt: Add -mfsgsbase, -mrdrnd and -mf16c.

	* config/i386/immintrin.h (_rdrand_u16): New.
	(_rdrand_u32): Likewise.
	(_readfsbase_u32): Likewise.
	(_readfsbase_u64): Likewise.
	(_readgsbase_u32): Likewise.
	(_readgsbase_u64): Likewise.
	(_writefsbase_u32): Likewise.
	(_writefsbase_u64): Likewise.
	(_writegsbase_u32): Likewise.
	(_writegsbase_u64): Likewise.
	(_rdrand_u64): Likewise.
	(_cvtsh_ss): Likewise.
	(_mm_cvtph_ps): Likewise.
	(_mm256_cvtph_ps): Likewise.
	(_cvtss_sh): Likewise.
	(_mm_cvtps_ph): Likewise.
	(_mm256_cvtps_ph): Likewise.

	* config/i386/sse.md (vcvtph2ps): New.
	(*vcvtph2ps_load): Likewise.
	(vcvtph2ps256): Likewise.
	(vcvtps2ph): Likewise.
	(*vcvtps2ph): Likewise.
	(*vcvtps2ph_store): Likewise.
	(vcvtps2ph256): Likewise.

	* doc/extend.texi: Document FSGSBASE and RDRND built-in functions.

	* doc/invoke.texi: Document -mfsgsbase, -mrdrnd and -mf16c.

gcc/testsuite/

2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>

	AVX Programming Reference (June, 2010)
	* g++.dg/other/i386-2.C: Add -mfsgsbase -mrdrnd -mf16c.
	* g++.dg/other/i386-3.C: Likewise.
	* gcc.target/i386/sse-12.c: Likewise.

	* gcc.target/i386/f16c-check.h: New.
	* gcc.target/i386/rdfsbase-1.c: Likewise.
	* gcc.target/i386/rdfsbase-2.c: Likewise.
	* gcc.target/i386/rdgsbase-1.c: Likewise.
	* gcc.target/i386/rdgsbase-2.c: Likewise.
	* gcc.target/i386/rdrand-1.c: Likewise.
	* gcc.target/i386/rdrand-2.c: Likewise.
	* gcc.target/i386/rdrand-3.c: Likewise.
	* gcc.target/i386/vcvtph2ps-1.c: Likewise.
	* gcc.target/i386/vcvtph2ps-2.c: Likewise.
	* gcc.target/i386/vcvtph2ps-3.c: Likewise.
	* gcc.target/i386/vcvtps2ph-1.c: Likewise.
	* gcc.target/i386/vcvtps2ph-2.c: Likewise.
	* gcc.target/i386/vcvtps2ph-3.c: Likewise.
	* gcc.target/i386/wrfsbase-1.c: Likewise.
	* gcc.target/i386/wrfsbase-2.c: Likewise.
	* gcc.target/i386/wrgsbase-1.c: Likewise.
	* gcc.target/i386/wrgsbase-2.c: Likewise.

	* gcc.target/i386/sse-13.c: Add -mfsgsbase -mrdrnd -mf16c.
	(__builtin_ia32_vcvtps2ph): New.
	(__builtin_ia32_vcvtps2ph256): Likewise.

	* gcc.target/i386/sse-14.c: Add -mfsgsbase -mrdrnd -mf16c.
	Test _cvtss_sh, _mm_cvtps_ph and _mm256_cvtps_ph.

	* gcc.target/i386/sse-22.c: Add fsgsbase,rdrnd,f16c.
	Test _cvtss_sh, _mm_cvtps_ph and _mm256_cvtps_ph.

	* gcc.target/i386/sse-23.c (__builtin_ia32_vcvtps2ph): New.
	(__builtin_ia32_vcvtps2ph256): Likewise.
	Add fsgsbase,rdrnd,f16c.

	* lib/target-supports.exp (check_effective_target_f16c): New.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161855 138bc75d-0d04-0410-961f-82ee72b054a4

	(override_options): Initialize it.
	(ix86_expand_prologue): Use it.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161851 138bc75d-0d04-0410-961f-82ee72b054a4

	* config/ia64/t-ia64 (ia64.o): Depend on reload.h.
	* config/ia64/ia64.c Include reload.h.
	(ia64_memory_move_cost): New function.
	(TARGET_MEMORY_MOVE_COST): Define.
	(ia64_register_move_cost): Replace MEMORY_MOVE_COST with
	memory_move_cost.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161845 138bc75d-0d04-0410-961f-82ee72b054a4

	* arm-modes.def (CC_NOTB): Don't define.
	* config/arm/arm.md (arm_adddi3): Generate canonical RTL.
	(adddi_sesidi_di, adddi_zesidi_di): Likewise.
	(LTUGEU): New code_iterator.
	(cnb, optab): New corresponding code_attrs.
	(addsi3_carryin_<optab>): Renamed from addsi3_carryin.  Change pattern
	to canonical form.  Operands 1 and 2 are commutative.  Parametrize
	using LTUGEU.
	(addsi3_carryin_shift_<optab>): Likewise.
	(addsi3_carryin_alt2_<optab>): Renamed from addsi3_carryin_alt2.
	Operands 1 and 2 are commutative.  Parametrize using LTUGEU.
	(addsi3_carryin_alt1, addsi3_carryin_alt3): Remove.
	(subsi3_compare): Renamed from subsi3_compare0_c.  Change CC_NOTB to
	CC.
	(arm_subsi3_insn): Allow constants for operand 0.
	(compare_scc peephole for eq case): New.
	(compare_scc splitters): Change CC_NOTB to CC.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161831 138bc75d-0d04-0410-961f-82ee72b054a4

	* tree-ssa-loop-im.c (for_each_index): Do not handle
	ALIGN_INDIRECT_REF.
	(gen_lsm_tmp_name): Likewise.
	* tree-dump.c (dequeue_and_dump): Likewise.
	* tree-pretty-print.c (dump_generic_node): Likewise.
	(op_code_prio): Likewise.
	(op_symbol_code): Likewise.
	* tree.c (staticp): Likewise.
	(build1_stat): Likewise.
	* tree.h (INDIRECT_REF_P): Likewise.
	* fold-const.c (maybe_lvalue_p): Likewise.
	(operand_equal_p): Likewise.
	* tree-ssa-sccvn.c (copy_reference_ops_from_ref): Likewise.
	(ao_ref_init_from_vn_reference): Likewise.
	* tree-ssa-loop-ivopts.c (idx_find_step): Likewise.
	(find_interesting_uses_address): Likewise.
	* dwarf2out.c (loc_list_from_tree): Likewise.
	* gimplify.c (gimplify_expr): Likewise.
	* tree-eh.c (tree_could_trap_p): Likewise.
	* emit-rtl.c (set_mem_attributes_minus_bitpos): Likewise.
	* cfgexpand.c (expand_debug_expr): Likewise.
	* tree-ssa-pre.c (create_component_ref_by_pieces_1): Likewise.
	* tree-ssa-loop-prefetch.c (idx_analyze_ref): Likewise.
	* tree-cfg.c (verify_types_in_gimple_min_lval): Likewise.
	* config/rs6000/rs6000 (rs6000_check_sdmode): Likewise.
	* tree-ssa-operands.c (get_expr_operands): Likewise.
	* expr.c (safe_from_p): Likewise.
	(expand_expr_real_1): Likewise.  TER BIT_AND_EXPRs into MEM_REFs.
	* tree-vect-data-refs.c (vect_setup_realignment): Build
	BIT_AND_EXPR and MEM_REF instead of ALIGN_INDIRECT_REF.
	* tree-vect-stmts.c (vectorizable_load): Likewise.
	* tree.def (ALIGN_INDIRECT_REF): Remove.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161830 138bc75d-0d04-0410-961f-82ee72b054a4

	* config/rs6000/e500crtsav64gprctr.asm: Likewise.
	* config/rs6000/e500crtres64gprctr.asm: Likewise. Add FUNC_END
	directives.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161828 138bc75d-0d04-0410-961f-82ee72b054a4

	PR bootstrap/44820
	* config/arm/arm.c (arm_attr_length_move_neon): Delete regno.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161822 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/

2010-07-04  H.J. Lu  <hongjiu.lu@intel.com>

	PR rtl-optimization/44695
	* config/i386/i386.md (extract_code): Removed.
	(<u>divmodqi4): Likewise.
	(divmodqi4): New.
	(udivmodqi4): Likewise.
	(divmodhiqi3): Change div/mod to HImode and extend operand 2 to
	HImode.
	(udivmodhiqi3): Likewise.

gcc/testsuite/

2010-07-04  H.J. Lu  <hongjiu.lu@intel.com>

	PR rtl-optimization/44695
	* gcc.dg/torture/pr44695.c: New.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161813 138bc75d-0d04-0410-961f-82ee72b054a4

	* optabs.h (reload_in_optab, reload_out_optab, code_to_optab)
	(vcond_gen_code, vcondu_gen_code, movmem_optab, setmem_optab)
	(cmpstr_optab, cmpstrn_optab, cmpmem_optab, sync_add_optab)
	(sync_sub_optab, sync_ior_optab, sync_and_optab, sync_xor_optab)
	(sync_nand_optab, sync_old_add_optab, sync_old_sub_optab)
	(sync_old_ior_optab, sync_old_and_optab, sync_old_xor_optab)
	(sync_old_nand_optab, sync_new_add_optab, sync_new_sub_optab)
	(sync_new_ior_optab, sync_new_and_optab, sync_new_xor_optab)
	(sync_new_nand_optab): Redefine as macros.
	(sync_compare_and_swap, sync_lock_test_and_set, sync_lock_release):
	Delete.
	(direct_optab_index): New enum.
	(direct_optab_d): New structure.
	(direct_optab): New typedef.
	(direct_optab_table): Declare.
	(direct_optab_handler, set_direct_optab_handler): New functions.
	(sync_compare_and_swap_optab, sync_lock_test_and_set_optab)
	(sync_lock_release_optab): New macros.
	* optabs.c (direct_optab_table): New variable.
	(movcc_gen_code, vcond_gen_code, vcondu_gen_code): Delete.
	(prepare_cmp_insn): Use direct_optab_handler for cmpmem_optab,
	cmpstr_optab and cmpstrn_optab.
	(emit_conditional_move): Likewise for movcc_optab.
	(can_conditionally_move_p): Likewise for movcc_gen_code.
	(init_insn_codes): Clear direct_optab_table.
	(init_optabs): Don't initialize the new "direct optabs" here.
	(get_vcond_icode): Use direct_optab_handler for vcondu_gen_code and
	vcond_gen_code.
	(expand_val_compare_and_swap): Likewise sync_compare_and_swap_optab.
	(expand_bool_compare_and_swap): Likewise sync_compare_and_swap_optab.
	(expand_compare_and_swap_loop): Likewise sync_compare_and_swap_optab.
	(expand_sync_operation): Likewise other sync_*_optabs.
	(expand_sync_fetch_operation): Likewise.  Rename sync_compare_and_swap
	to sync_compare_and_swap_optab.
	(expand_sync_lock_test_and_set): Use direct_optab_handler for
	sync_lock_test_and_set and sync_compare_and_swap, adding "_optab"
	to the names of both.
	* builtins.c (expand_builtin_strcmp): Use direct_optab_handler for
	cmpstr_optab and cmpstrn_optab.
	(expand_builtin_lock_release): Likewise sync_lock_release.
	* expr.c (movmem_optab, setmem_optab, cmpstr_optab, cmpstrn_optab)
	(cmpmem_optab, sync_add_optab, sync_sub_optab, sync_ior_optab)
	(sync_and_optab, sync_xor_optab, sync_nand_optab, sync_old_add_optab)
	(sync_old_sub_optab, sync_old_ior_optab, sync_old_and_optab)
	(sync_old_xor_optab, sync_old_nand_optab, sync_new_add_optab)
	(sync_new_sub_optab, sync_new_ior_optab, sync_new_and_optab)
	(sync_new_xor_optab, sync_new_nand_optab, sync_compare_and_swap)
	(sync_lock_test_and_set, sync_lock_release): Delete.
	(emit_block_move_via_movmem): Use direct_optab_handler for movmem_optab.
	(emit_block_move_via_setmem): Use direct_optab_handler for setmem_optab.
	* genopinit.c (optabs): Use set_direct_optab_handler for the new
	macro optabs.
	* omp-low.c (expand_omp_atomic_fetch_op): Update the type of
	the "optab" local variable.  Use direct_optab_handler for optab and
	sync_compare_and_swap_optab.
	* reload1.c (reload_in_optab, reload_out_optab): Delete.
	* targhooks.c (default_secondary_reload): Use direct_optab_handler for
	reload_in_optab and reload_out_optab.
	* config/alpha/alpha.c (alpha_secondary_reload): Likewise.
	* config/frv/frv.c (frv_alloc_temp_reg): Likewise.
	* config/pa/pa.c (pa_secondary_reload): Likewise.
	* java/builtins.c (compareAndSwapInt_builtin): Use direct_optab_handler
	for sync_compare_and_swap, renaming it to sync_compare_and_swap_optab.
	(compareAndSwapLong_builtin, compareAndSwapObject_builtin): Likewise.
	(VMSupportsCS8_builtin): Likewise.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161810 138bc75d-0d04-0410-961f-82ee72b054a4

	* optabs.h (optab_handler, convert_optab_handler): Turn into
	inline functions that return an insn code.
	(set_optab_handler, set_convert_optab_handler): New functions.
	* builtins.c: Replace optab_handler(X)->insn_code with
	optab_handler or set_optab_handler thoughout.  Likewise
	convert_optab_handler(X)->insn_code with convert_optab_handler
	and set_convert_optab_handler.
	* expmed.c, expr.c, genopinit.c, ifcvt.c, optabs.c, reload.c,
	reload1.c, stmt.c, targhooks.c, tree-ssa-loop-prefetch.c,
	tree-ssa-math-opts.c, tree-vect-data-refs.c, tree-vect-generic.c,
	tree-vect-loop.c, tree-vect-patterns.c, tree-vect-slp.c,
	tree-vect-stmts.c, config/m32c/m32c.c, config/rs6000/rs6000.c,
	config/spu/spu.c: Likewise.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161808 138bc75d-0d04-0410-961f-82ee72b054a4

	* doc/tm.texi.in (TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST):
	Document new arguments.
	* doc/tm.texi: Regenerate.
	* targhooks.c (default_builtin_vectorization_cost): Add new arguments.
	Handle unaligned store.
	* targhooks.h (default_builtin_vectorization_cost): Add new arguments.
	* target.def (builtin_vectorization_cost): Add new arguments.
	* target.h (enum vect_cost_for_stmt): Add unaligned_store.
	* tree-vect-loop-manip.c (vect_gen_niters_for_prolog_loop): Take number
	of iterations of prolog loop directly from LOOP_PEELING_FOR_ALIGNMENT.
	(vect_vfa_segment_size): Fix indentation.
	* tree-vectorizer.h (struct _vect_peel_info): New.
	(struct _vect_peel_extended_info): New.
	(struct _loop_vec_info): Add new field for peeling hash table and a
	macro for its access.
	(VECT_MAX_COST): Define.
	(vect_get_load_cost): Declare.
	(vect_get_store_cost, vect_get_known_peeling_cost, 
	vect_get_single_scalar_iteraion_cost): Likewise.
	(vect_supportable_dr_alignment): Add new argument.
	* tree-vect-loop.c (new_loop_vec_info): Initialize peeling hash table
	field.
	(destroy_loop_vec_info): Free peeling hash table.
	(vect_analyze_loop_form): Update call to builtin_vectorization_cost.
	(vect_analyze_loop): Move vect_enhance_data_refs_alignment before
	vect_analyze_slp. Fix indentation.
	(vect_get_single_scalar_iteraion_cost): New function.
	(vect_get_known_peeling_cost): Likewise.
	(vect_estimate_min_profitable_iters): Rename byte_misalign to npeel. 
	Call vect_get_single_scalar_iteraion_cost instead of cost_for_stmt per 
	statement. Move outside cost calculation inside unknown peeling case.
	Call vect_get_known_peeling_cost for known amount of peeling.
	* tree-vect-data-refs.c (vect_compute_data_ref_alignment): Add data
	reference to the print message of forced alignment.
	(vect_verify_datarefs_alignment): Update call to 
	vect_supportable_dr_alignment.
	(vect_get_data_access_cost): New function.
	(vect_peeling_hash, vect_peeling_hash_eq, vect_peeling_hash_insert,
	vect_peeling_hash_get_most_frequent, vect_peeling_hash_get_lowest_cost,
	vect_peeling_hash_choose_best_peeling): Likewise.
	(vect_enhance_data_refs_alignment): Fix documentation. Use hash table
	to store all the accesses in the loop and find best possible access to
	align using peeling for known alignment case. For unknown alignment
	check if stores are preferred or if peeling is worthy.
	(vect_find_same_alignment_drs): Analyze pairs of loads too.
	(vect_supportable_dr_alignment): Add new argument and check aligned
	accesses according to it. 
	* tree-vect-stmts.c (vect_get_stmt_cost): New function.
	(cost_for_stmt): Call vect_get_stmt_cost. 
	(vect_model_simple_cost): Likewise.
	(vect_model_store_cost): Call vect_get_stmt_cost. Call 
	vect_get_store_cost to calculate the cost of the statement.
	(vect_get_store_cost): New function.
	(vect_model_load_cost): Call vect_get_stmt_cost. Call 
	vect_get_load_cost to calculate the cost of the statement.
	(vect_get_load_cost): New function.
	(vectorizable_store): Update call to vect_supportable_dr_alignment.
	(vectorizable_load): Likewise.
	* config/spu/spu.c (spu_builtin_vectorization_cost): Add new
	arguments. 
	* config/i386/i386.c (ix86_builtin_vectorization_cost): Add new
	arguments. Handle unaligned store.
	* config/rs6000/rs6000.c (rs6000_builtin_vectorization_cost): New.
	(rs6000_builtin_support_vector_misalignment): Return true for word and
	double word alignments for VSX.
	* tree-vect-slp.c (vect_build_slp_tree): Update calls to 
	vect_supportable_dr_alignment and builtin_vectorization_cost.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161797 138bc75d-0d04-0410-961f-82ee72b054a4

	* config/pa/predicates.md (prefetch_cc_operand): Remove.
	(prefetch_nocc_operand): Likewise.
	* config/pa/pa.md (prefetch): Revise expander to use prefetch_20.
	(prefetch_20): New insn.
	(prefetch_cc): Remove.
	(prefetch_nocc): Likewise.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161786 138bc75d-0d04-0410-961f-82ee72b054a4

	* config/pa/pa.h (GO_IF_LEGITIMATE_ADDRESS): Reject LABEL_REF.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161781 138bc75d-0d04-0410-961f-82ee72b054a4

	* config/arm/arm-protos.h (arm_attr_length_move_neon): Declare.
	* config/arm/neon.md (define_mode_attr V_slen): Remove.
	(neon_mov<mode> for VSTRUCT): Use arm_attr_length_move_neon
	to compute length attribute.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161776 138bc75d-0d04-0410-961f-82ee72b054a4

	as predicate for operand 1 and remove its constraint.
	* config/arm/predicates.md (vfp_register_operand): New.
	* config/arm/arm.md (*push_multi): Remove the constraint of
	operand 1.
	(*push_fp_multi): Likewise.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161775 138bc75d-0d04-0410-961f-82ee72b054a4

	* config/i386/i386.c (override_options): Revert accidental commit.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161772 138bc75d-0d04-0410-961f-82ee72b054a4

	    Julian Brown  <julian@codesourcery.com>
	    Sandra Loosemore <sandra@codesourcery.com>

	gcc/
	* config/arm/arm.c (arm_canonicalize_comparison): Canonicalize DImode
	comparisons.  Adjust to take both operands.
	(arm_select_cc_mode): Handle DImode comparisons.
	(arm_gen_compare_reg): Generate a scratch register for DImode
	comparisons which require one.  Use xor for Thumb equality checks.
	(arm_const_double_by_immediates): New.
	(arm_print_operand): Allow 'Q' and 'R' for constants.
	(get_arm_condition_code): Handle new CC_CZmode and CC_NCVmode.
	* config/arm/arm.h (CANONICALIZE_COMPARISON): Always use
	arm_canonicalize_comparison.
	* config/arm/arm-modes.def: Add CC_CZmode and CC_NCVmode.
	* config/arm/arm-protos.h (arm_canonicalize_comparison): Update
	prototype.
	(arm_const_double_by_immediates): Declare.
	* config/arm/constraints.md (Di): New constraint.
	* config/arm/predicates.md (arm_immediate_di_operand)
	(arm_di_operand, cmpdi_operand): New.
	* config/arm/arm.md (cbranchdi4): Handle non-Cirrus also.
	(*arm_cmpdi_insn, *arm_cmpdi_unsigned)
	(*arm_cmpdi_zero, *thumb_cmpdi_zero): New insns.
	(cstoredi4): Handle non-Cirrus also.

	gcc/testsuite/
	* gcc.c-torture/execute/20100416-1.c: New test case.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161764 138bc75d-0d04-0410-961f-82ee72b054a4

	    Sandra Loosemore <sandra@codesourcery.com>

	PR target/43703

	gcc/
	* config/arm/vec-common.md (add<mode>3, sub<mode>3, smin<mode>3)
	(smax<mode>3): Disable for NEON float modes when
	flag_unsafe_math_optimizations is false.
	* config/arm/neon.md (*add<mode>3_neon, *sub<mode>3_neon)
	(*mul<mode>3_neon)
	(mul<mode>3add<mode>_neon, mul<mode>3neg<mode>add<mode>_neon)
	(reduc_splus_<mode>, reduc_smin_<mode>, reduc_smax_<mode>): Disable
	for NEON float modes when flag_unsafe_math_optimizations is false.
	(quad_halves_<code>v4sf): Only enable if flag_unsafe_math_optimizations
	is true.
	* doc/invoke.texi (ARM Options): Add note about floating point
	vectorization requiring -funsafe-math-optimizations.

	gcc/testsuite/
	* gcc.dg/vect/vect.exp: Add -ffast-math for NEON.
	* gcc.dg/vect/vect-reduc-6.c: Add XFAIL for NEON.




git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161763 138bc75d-0d04-0410-961f-82ee72b054a4

	    Julian Brown  <julian@codesourcery.com>

	gcc/
	* config/arm/neon.md (UNSPEC_VABA): Delete.
	(UNSPEC_VABAL): Delete.
	(UNSPEC_VABS): Delete.
	(UNSPEC_VMUL_N): Delete.
	(adddi3_neon): New.
	(subdi3_neon): New.
	(mul<mode>3add<mode>_neon): Make the pattern named.
	(mul<mode>3neg<mode>add<mode>_neon): Likewise.
	(neon_vadd<mode>): Replace with define_expand, and move the remaining
	unspec parts...
	(neon_vadd<mode>_unspec): ...to this.
	(neon_vmla<mode>, neon_vmla<mode>_unspec): Likewise.
	(neon_vlms<mode>, neon_vmls<mode>_unspec): Likewise.
	(neon_vsub<mode>, neon_vsub<mode>_unspec): Likewise.
	(neon_vaba<mode>): Rewrite in terms of vabd.
	(neon_vabal<mode>): Rewrite in terms of vabdl.
	(neon_vabs<mode>): Rewrite without unspec.
	* config/arm/arm.md (*arm_adddi3): Disable for TARGET_NEON.
	(*arm_subdi3): Likewise.
	* config/arm/neon.ml (Vadd, Vsub): Split out 64-bit variants and add
	No_op attribute to disable assembly output checks.
	* config/arm/arm_neon.h: Regenerated.
	* doc/arm-neon-intrinsics.texi: Regenerated.

	gcc/testsuite/
	* gcc.target/arm/neon/vadds64.c: Regenerated.
	* gcc.target/arm/neon/vaddu64.c: Regenerated.
	* gcc.target/arm/neon/vsubs64.c: Regenerated.
	* gcc.target/arm/neon/vsubu64.c: Regenerated.
	* gcc.target/arm/neon-vmla-1.c: Add -ffast-math to options.
	* gcc.target/arm/neon-vmls-1.c: Likewise.
	* gcc.target/arm/neon-vsubs64.c: New execution test.
	* gcc.target/arm/neon-vsubu64.c: New execution test.
	* gcc.target/arm/neon-vadds64.c: New execution test.
	* gcc.target/arm/neon-vaddu64.c: New execution test.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161762 138bc75d-0d04-0410-961f-82ee72b054a4

	when passing DECL_BY_REFERENCE produce *<retval> = fncall.part ()
	(execute_split_functions): Do not care about DECL_BY_REFERENCE.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161756 138bc75d-0d04-0410-961f-82ee72b054a4

	gcc/
	* config/arm/neon.md (UNSPEC_VAND): Delete.
	(UNSPEC_VBIC): Delete.
	(UNSPEC_VCLZ): Delete.
	(UNSPEC_VCNT): Delete.
	(UNSPEC_VEOR): Delete.
	(UNSPEC_VORN): Delete.
	(UNSPEC_VORR): Delete.
	(iordi3_neon): Rewrite RTL without unspec.  Add alternatives to handle
	core registers too.
	(anddi3_neon): Likewise.
	(orndi3_neon): Likewise.
	(bicdi3_neon): Likewise.
	(xordi3_neon): Likewise.
	(neon_vclz<mode>): Rewrite as define_expand and clz<mode>2 to get
	rid of unspec and handle unused operand.
	(neon_vcnt<mode>): Similarly, with popcount<mode>2.
	* config/arm/predicates.md (imm_for_neon_logic_operand):
	Require TARGET_NEON.
	(imm_for_neon_inv_logic_operand): Likewise.
	* config/arm/arm.md (define_split for logical_binary_operator): 
	Disable for NEON registers.
	(anddi3): Add new define_expand, and rename the insn.  Disable
	this insn for NEON, where anddi3_neon now applies.
	(*anddi_notdi_di): Disable for TARGET_NEON, where bicdi3_neon applies.
	(iordi3): As for anddi3.
	(xordi3): Likewise.
	* config/arm/neon.ml (Vand): Split DImode variants and mark them
	as No_op to disable testing for exact instruction match.
	(Vorr): Likewise.
	(Veor): Likewise.
	(Vbic): Likewise.
	(Vorn): Likewise.
	* config/arm/arm_neon.h: Regenerated.
	* doc/arm-neon-intrinsics.texi: Regenerated.

	gcc/testsuite/
	* gcc.target/arm/neon-vands64.c: New.
	* gcc.target/arm/neon-vandu64.c: New.
	* gcc.target/arm/neon-vbics64.c: New.
	* gcc.target/arm/neon-vbicu64.c: New.
	* gcc.target/arm/neon-veors64.c: New.
	* gcc.target/arm/neon-veoru64.c: New.
	* gcc.target/arm/neon-vorns64.c: New.
	* gcc.target/arm/neon-vornu64.c: New.
	* gcc.target/arm/neon-vorrs64.c: New.
	* gcc.target/arm/neon-vorru64.c: New.
	* gcc.target/arm/neon/vands64.c: Regenerated.
	* gcc.target/arm/neon/vandu64.c: Regenerated.
	* gcc.target/arm/neon/vbics64.c: Regenerated.
	* gcc.target/arm/neon/vbicu64.c: Regenerated.
	* gcc.target/arm/neon/veors64.c: Regenerated.
	* gcc.target/arm/neon/veoru64.c: Regenerated.
	* gcc.target/arm/neon/vorns64.c: Regenerated.
	* gcc.target/arm/neon/vornu64.c: Regenerated.
	* gcc.target/arm/neon/vorrs64.c: Regenerated.
	* gcc.target/arm/neon/vorru64.c: Regenerated.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161755 138bc75d-0d04-0410-961f-82ee72b054a4

	* explow.c (emit_stack_probe): Make global.
	(anti_adjust_stack_and_probe): Fix comments.
	* config/sparc/linux.h (STACK_CHECK_STATIC_BUILTIN): Define to 1.
	* config/sparc/linux64.h (STACK_CHECK_STATIC_BUILTIN): Likewise.
	* config/sparc/sol2.h (STACK_CHECK_STATIC_BUILTIN): Likewise.
	* config/sparc/sparc.c: Include except.h.
	(sparc_emit_probe_stack_range): New function.
	(output_probe_stack_range): Likewise.
	(sparc_expand_prologue): Invoke sparc_emit_probe_stack_range if static
	built-in stack checking is enabled.
	* config/sparc/sparc-protos.h (output_probe_stack_range): Declare.
	* config/sparc/sparc.md (UNSPECV_PROBE_STACK_RANGE): New constant.
	(probe_stack_range): New insn.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161749 138bc75d-0d04-0410-961f-82ee72b054a4

	* config/pa/pa.c (hppa_gimplify_va_arg_expr): Use pointer arithmetic
	for argument alignment.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161746 138bc75d-0d04-0410-961f-82ee72b054a4

* config/m68k/m68k.c (m68k_expand_prologue): Remove set but not
used variable insn.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161741 138bc75d-0d04-0410-961f-82ee72b054a4

	* config/arm/arm.c (thumb1_rtx_costs): Improve support for SIGN_EXTEND
	and ZERO_EXTEND.
	(arm_rtx_costs_1): Likewise.
	(arm_size_rtx_costs): Use arm_rtx_costs_1 for these codes.
	* config/arm/arm.md (is_arch6): New attribute.
	(zero_extendhisi2, zero_extendqisi2, extendhisi2,
	extendqisi2): Tighten the code somewhat, avoiding invalid
	RTL to occur in the expander patterns.
	(thumb1_zero_extendhisi2): Merge with thumb1_zero_extendhisi2_v6.
	(thumb1_zero_extendhisi2_v6): Delete.
	(thumb1_extendhisi2): Merge with thumb1_extendhisi2_v6.
	(thumb1_extendhisi2_v6): Delete.
	(thumb1_extendqisi2): Merge with thumb1_extendhisi2_v6.
	(thumb1_extendqisi2_v6): Delete.
	(zero_extendhisi2 for register input splitter): New.
	(zero_extendqisi2 for register input splitter): New.
	(thumb1_extendhisi2 for register input splitter): New.
	(extendhisi2 for register input splitter): New.
	(extendqisi2 for register input splitter): New.
	(TARGET_THUMB1 extendqisi2 for memory input splitter): New.
	(arm_zero_extendhisi2): Allow nonimmediate_operand for operand 1,
	and add support for a register alternative requiring a split.
	(thumb1_zero_extendqisi2): Likewise.
	(arm_zero_extendqisi2): Likewise.
	(arm_extendhisi2): Likewise.
	(arm_extendqisi2): Likewise.

testsuite/
	PR target/42172
	* gcc.target/arm/pr42172-1.c: New test.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161726 138bc75d-0d04-0410-961f-82ee72b054a4

	* config/arm/arm-modes.def (CC_NOTB): New mode.
	* config/arm/arm.c (get_arm_condition_code): Handle it.
	* config/arm/thumb2.md (thumb2_compare_scc): Delete pattern.
	* config/arm/arm.md (subsi3_compare0_c): New pattern.
	(compare_scc): Now a define_and_split.  Add a number of extra
	splitters before it.

testsuite/
	PR target/42835
	* gcc.target/arm/pr42835.c: New test.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161725 138bc75d-0d04-0410-961f-82ee72b054a4

	gcc/
	* config/arm/arm.c (neon_vdup_constant): Expand into canonical RTL
	instead of an unspec.
	(neon_expand_vector_init): Likewise.
	* config/arm/neon.md (UNSPEC_VCOMBINE): Delete.
	(UNSPEC_VDUP_LANE): Delete.
	(UNSPEC VDUP_N): Delete.
	(UNSPEC_VGET_HIGH): Delete.
	(UNSPEC_VGET_LANE): Delete.
	(UNSPEC_VGET_LOW): Delete.
	(UNSPEC_VMVN): Delete.
	(UNSPEC_VSET_LANE): Delete.
	(V_double_vector_mode): New.
	(vec_set<mode>_internal): Make code emitted match that for the
	corresponding intrinsics.
	(vec_setv2di_internal): Likewise.
	(neon_vget_lanedi): Rewrite to expand into emit_move_insn.
	(neon_vget_lanev2di): Rewrite to expand into vec_extractv2di.
	(neon_vset_lane<mode>): Combine double and quad patterns and
	expand into vec_set<mode>_internal instead of UNSPEC_VSET_LANE.
	(neon_vset_lanedi): Rewrite to expand into emit_move_insn.
	(neon_vdup_n<mode>): Rewrite RTL without unspec.
	(neon_vdup_ndi): Rewrite as define_expand and use emit_move_insn.
	(neon_vdup_nv2di): Rewrite RTL without unspec and merge with
	with neon_vdup_lanev2di, adjusting the pattern from the latter
	to be predicable for consistency.
	(neon_vdup_lane<mode>_internal): New.
	(neon_vdup_lane<mode>): Turn into a define_expand and rewrite
	to avoid using an unspec.
	(neon_vdup_lanedi): Rewrite RTL pattern to avoid unspec.
	(neon_vdup_lanev2di): Turn into a define_expand.
	(neon_vcombine): Rewrite pattern to eliminate UNPSEC_VCOMBINE.
	(neon_vget_high<mode>): Replace with....
	(neon_vget_highv16qi): New pattern using canonical RTL.
	(neon_vget_highv8hi): Likewise.
	(neon_vget_highv4si): Likewise.
	(neon_vget_highv4sf): Likewise.
	(neon_vget_highv2di): Likewise.
	(neon_vget_low<mode>): Replace with....
	(neon_vget_lowv16qi): New pattern using canonical RTL.
	(neon_vget_lowv8hi): Likewise.
	(neon_vget_lowv4si): Likewise.
	(neon_vget_lowv4sf): Likewise.
	(neon_vget_lowv2di): Likewise.

	* config/arm/neon.ml (Vget_lane): Add No_op attribute to suppress
	test for this emitting vmov.
	(Vset_lane): Likewise.
	(Vdup_n): Likewise.
	(Vmov_n): Likewise.

	* doc/arm-neon-intrinsics.texi: Regenerated.

	gcc/testsuite/
	* gcc.target/arm/neon/vdup_ns64.c: Regenerated.
	* gcc.target/arm/neon/vdup_nu64.c: Regenerated.
	* gcc.target/arm/neon/vdupQ_ns64.c: Regenerated.
	* gcc.target/arm/neon/vdupQ_nu64.c: Regenerated.
	* gcc.target/arm/neon/vmov_ns64.c: Regenerated.
	* gcc.target/arm/neon/vmov_nu64.c: Regenerated.
	* gcc.target/arm/neon/vmovQ_ns64.c: Regenerated.
	* gcc.target/arm/neon/vmovQ_nu64.c: Regenerated.
	* gcc.target/arm/neon/vget_lanes64.c: Regenerated.
	* gcc.target/arm/neon/vget_laneu64.c: Regenerated.
	* gcc.target/arm/neon/vset_lanes64.c: Regenerated.
	* gcc.target/arm/neon/vset_laneu64.c: Regenerated.
	* gcc.target/arm/neon-vdup_ns64.c: New.
	* gcc.target/arm/neon-vdup_nu64.c: New.
	* gcc.target/arm/neon-vdupQ_ns64.c: New.
	* gcc.target/arm/neon-vdupQ_nu64.c: New.
	* gcc.target/arm/neon-vdupQ_lanes64.c: New.
	* gcc.target/arm/neon-vdupQ_laneu64.c: New.
	* gcc.target/arm/neon-vmov_ns64.c: New.
	* gcc.target/arm/neon-vmov_nu64.c: New.
	* gcc.target/arm/neon-vmovQ_ns64.c: New.
	* gcc.target/arm/neon-vmovQ_nu64.c: New.
	* gcc.target/arm/neon-vget_lanes64.c: New.
	* gcc.target/arm/neon-vget_laneu64.c: New.
	* gcc.target/arm/neon-vset_lanes64.c: New.
	* gcc.target/arm/neon-vset_laneu64.c: New.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161720 138bc75d-0d04-0410-961f-82ee72b054a4

	gcc/
	* config/arm/neon.md (vec_extractv2di): Correct error in register
	numbering to reconcile with neon_vget_lanev2di.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161719 138bc75d-0d04-0410-961f-82ee72b054a4

 
	* config/s390/s390.c (override_options): Adopt prefetching
	at -O3 to handle flag_prefetch_loop_arrays as a tristate.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161709 138bc75d-0d04-0410-961f-82ee72b054a4

	PR target/44707
	* config/rs6000/rs6000.c (rs6000_legitimize_reload_address): Recognize
	(lo_sum (high ...) ...) patterns generated by earlier passes.

testsuite/ChangeLog:

	PR target/44707
	* gcc.c-torture/compile/pr44707.c: New test.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161703 138bc75d-0d04-0410-961f-82ee72b054a4

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161667 138bc75d-0d04-0410-961f-82ee72b054a4

        * config/ia64/ia64.c (ia64_register_move_cost): Remove stray '{'.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161658 138bc75d-0d04-0410-961f-82ee72b054a4