* pa.md (shadd height reduction patterns/splitters): Remove.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@35442 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog

+Thu Aug  3 01:05:32 2000  Jeffrey A Law  (law@cygnus.com)
+
+	* pa.md (shadd height reduction patterns/splitters): Remove.
+
 2000-08-02  Jim Wilson  <wilson@cygnus.com>
 
 	* config/ia64/ia64-protos.h (flag_ssa): Declare.

gcc/config/pa/pa.md

@@ -5166,73 +5166,6 @@
   [(set_attr "type" "binary")
    (set_attr "length" "4")])
 
-;; This anonymous pattern and splitter wins because it reduces the latency
-;; of the shadd sequence without increasing the latency of the shift.
-;;
-;; We want to make sure and split up the operations for the scheduler since
-;; these instructions can (and should) schedule independently.
-;;
-;; It would be clearer if combine used the same operator for both expressions,
-;; it's somewhat confusing to have a mult in ine operation and an ashift
-;; in the other.
-;;
-;; If this pattern is not split before register allocation, then we must expose
-;; the fact that operand 4 is set before operands 1, 2 and 3 have been read.
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
-			  (match_operand:SI 3 "shadd_operand" ""))
-		 (match_operand:SI 1 "register_operand" "r")))
-   (set (match_operand:SI 4 "register_operand" "=&r")
-	(ashift:SI (match_dup 2)
-		   (match_operand:SI 5 "const_int_operand" "i")))]
-  "(INTVAL (operands[5]) == exact_log2 (INTVAL (operands[3]))
-    && ! (reg_overlap_mentioned_p (operands[4], operands[2])))"
-  "#"
-  [(set_attr "type" "binary")
-   (set_attr "length" "8")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
-			  (match_operand:SI 3 "shadd_operand" ""))
-		 (match_operand:SI 1 "register_operand" "r")))
-   (set (match_operand:SI 4 "register_operand" "=&r")
-	(ashift:SI (match_dup 2)
-		   (match_operand:SI 5 "const_int_operand" "i")))]
-  "INTVAL (operands[5]) == exact_log2 (INTVAL (operands[3]))"
-  [(set (match_dup 4) (ashift:SI (match_dup 2) (match_dup 5)))
-   (set (match_dup 0) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
-			       (match_dup 1)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
-			  (match_operand:DI 3 "shadd_operand" ""))
-		 (match_operand:DI 1 "register_operand" "r")))
-   (set (match_operand:DI 4 "register_operand" "=&r")
-	(ashift:DI (match_dup 2)
-		   (match_operand:DI 5 "const_int_operand" "i")))]
-  "TARGET_64BIT && INTVAL (operands[5]) == exact_log2 (INTVAL (operands[3]))"
-  "#"
-  [(set_attr "type" "binary")
-   (set_attr "length" "8")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
-			  (match_operand:DI 3 "shadd_operand" ""))
-		 (match_operand:DI 1 "register_operand" "r")))
-   (set (match_operand:DI 4 "register_operand" "=&r")
-	(ashift:DI (match_dup 2)
-		   (match_operand:DI 5 "const_int_operand" "i")))]
-  "TARGET_64BIT && INTVAL (operands[5]) == exact_log2 (INTVAL (operands[3]))"
-  [(set (match_dup 4) (ashift:DI (match_dup 2) (match_dup 5)))
-   (set (match_dup 0) (plus:DI (mult:DI (match_dup 2) (match_dup 3))
-			       (match_dup 1)))]
-  "")
-
 (define_expand "ashlsi3"
   [(set (match_operand:SI 0 "register_operand" "")
 	(ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")