2003-09-04 Eric Christopher <echristo@redhat.com>

	* config/mips/mips.c (mips_expand_prologue): Convert to
	calls.struct_value_rtx hook.
	(reg_or_const_float_1_operand): New.
	* config/mips/mips.h: Update Comments.
	(mips_arg): Add reg_or_const_float_1_operand.
	* config/mips/mips.md (divdf3); Convert to expander.
	(divsf3): Ditto.
	(*divdf3): New pattern.
	(*divsf3): Ditto.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@71056 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog

+2003-09-04  Eric Christopher  <echristo@redhat.com>
+
+	* config/mips/mips.c (mips_expand_prologue): Convert to
+	calls.struct_value_rtx hook.
+	(reg_or_const_float_1_operand): New.
+	* config/mips/mips.h: Update Comments.
+	(mips_arg): Add reg_or_const_float_1_operand.
+	* config/mips/mips.md (divdf3); Convert to expander.
+	(divsf3): Ditto.
+	(*divdf3): New pattern.
+	(*divsf3): Ditto.
+
 Thu Sep  4 10:43:24 CEST 2003  Jan Hubicka  <jh@suse.cz>
 
 	* toplev.c (wrapup_global_declarations): Fix final pass in

gcc/config/mips/mips.c

@@ -1303,6 +1303,28 @@ reg_or_0_operand (rtx op, enum machine_mode mode)
     }
 }
 
+/* Accept a register or the floating point constant 1 in the appropriate mode.  */
+
+int
+reg_or_const_float_1_operand (rtx op, enum machine_mode mode)
+{
+  REAL_VALUE_TYPE d;
+
+  switch (GET_CODE (op))
+    {
+    case CONST_DOUBLE:
+      if (mode != GET_MODE (op)
+	  || (mode != DFmode && mode != SFmode))
+	return 0;
+
+      REAL_VALUE_FROM_CONST_DOUBLE (d, op);
+      return REAL_VALUES_EQUAL (d, dconst1);
+
+    default:
+      return register_operand (op, mode);
+    }
+}
+
 /* Accept the floating point constant 1 in the appropriate mode.  */
 
 int
@@ -6714,7 +6736,7 @@ mips_expand_prologue (void)
   /* If struct value address is treated as the first argument, make it so.  */
   if (aggregate_value_p (DECL_RESULT (fndecl), fndecl)
       && ! current_function_returns_pcc_struct
-      && struct_value_incoming_rtx == 0)
+      && targetm.calls.struct_value_rtx (fndecl, 0) == 0)
     {
       tree type = build_pointer_type (fntype);
       tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);

gcc/config/mips/mips.h

@@ -1415,12 +1415,7 @@ extern const struct mips_cpu_info *mips_tune_info;
    on the full register even if a narrower mode is specified.  */
 #define WORD_REGISTER_OPERATIONS
 
-/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
-   will either zero-extend or sign-extend.  The value of this macro should
-   be the code that says which one of the two operations is implicitly
-   done, NIL if none.
-
-   When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
+/* When in 64 bit mode, move insns will sign extend SImode and CCmode
    moves.  All other references are zero extended.  */
 #define LOAD_EXTEND_OP(MODE) \
   (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
@@ -2668,9 +2663,7 @@ typedef struct mips_args {
 
 /* Specify the machine mode that this machine uses
    for the index in the tablejump instruction.
-   ??? Using HImode in mips16 mode can cause overflow.  However, the
-   overflow is no more likely than the overflow in a branch
-   instruction.  Large functions can currently break in both ways.  */
+   ??? Using HImode in mips16 mode can cause overflow. */
 #define CASE_VECTOR_MODE \
   (TARGET_MIPS16 ? HImode : ptr_mode)
 
@@ -2808,6 +2801,7 @@ typedef struct mips_args {
   {"small_int",			{ CONST_INT }},				\
   {"mips_const_double_ok",	{ CONST_DOUBLE }},			\
   {"const_float_1_operand",	{ CONST_DOUBLE }},			\
+  {"reg_or_const_float_1_operand", { CONST_DOUBLE, REG}},               \
   {"simple_memory_operand",	{ MEM, SUBREG }},			\
   {"equality_op",		{ EQ, NE }},				\
   {"cmp_op",			{ EQ, NE, GT, GE, GTU, GEU, LT, LE,	\

gcc/config/mips/mips.md

@@ -2365,6 +2365,17 @@
 ;;  ....................
 ;;
 
+(define_expand "divdf3"
+  [(set (match_operand:DF 0 "register_operand" "")
+	(div:DF (match_operand:DF 1 "reg_or_const_float_1_operand" "")
+		(match_operand:DF 2 "register_operand" "")))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+{
+  if (const_float_1_operand (operands[1], DFmode))
+    if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
+      FAIL;
+})
+
 ;; This pattern works around the early SB-1 rev2 core "F1" erratum:
 ;;
 ;; If an mfc1 or dmfc1 happens to access the floating point register
@@ -2376,7 +2387,8 @@
 ;;
 ;; The workaround is to insert an unconditional 'mov' from/to the
 ;; long latency op destination register.
-(define_insn "divdf3"
+
+(define_insn "*divdf3"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(div:DF (match_operand:DF 1 "register_operand" "f")
 		(match_operand:DF 2 "register_operand" "f")))]
@@ -2395,6 +2407,17 @@
                       (const_int 4)))])
 
 
+(define_expand "divsf3"
+  [(set (match_operand:SF 0 "register_operand" "")
+	(div:SF (match_operand:SF 1 "reg_or_const_float_1_operand" "")
+		(match_operand:SF 2 "register_operand" "")))]
+  "TARGET_HARD_FLOAT"
+{
+  if (const_float_1_operand (operands[1], SFmode))
+    if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
+      FAIL;
+})
+
 ;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
 ;; "divdf3" comment for details).
 ;;
@@ -2406,7 +2429,7 @@
 ;; Therefore, we only allow div.s if not working around SB-1 rev2
 ;; errata, or if working around those errata and a slight loss of
 ;; precision is OK (i.e., flag_unsafe_math_optimizations is set).
-(define_insn "divsf3"
+(define_insn "*divsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(div:SF (match_operand:SF 1 "register_operand" "f")
 		(match_operand:SF 2 "register_operand" "f")))]