From 8eb3a05999b8b822a11bfc682e6214c1905a7d44 Mon Sep 17 00:00:00 2001
From: echristo <echristo@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Thu, 4 Sep 2003 09:55:33 +0000
Subject: [PATCH] 2003-09-04 Eric Christopher <echristo@redhat.com>
* config/mips/mips.c (mips_expand_prologue): Convert to
calls.struct_value_rtx hook.
(reg_or_const_float_1_operand): New.
* config/mips/mips.h: Update Comments.
(mips_arg): Add reg_or_const_float_1_operand.
* config/mips/mips.md (divdf3); Convert to expander.
(divsf3): Ditto.
(*divdf3): New pattern.
(*divsf3): Ditto.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@71056 138bc75d-0d04-0410-961f-82ee72b054a4
---
gcc/ChangeLog | 18 +++++++++++++++---
gcc/config/mips/mips.c | 24 +++++++++++++++++++++++-
gcc/config/mips/mips.h | 40 +++++++++++++++++-----------------------
gcc/config/mips/mips.md | 27 +++++++++++++++++++++++++--
4 files changed, 80 insertions(+), 29 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 31fad7db1a1..2b90b2a0a5b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2003-09-04 Eric Christopher <echristo@redhat.com>
+
+ * config/mips/mips.c (mips_expand_prologue): Convert to
+ calls.struct_value_rtx hook.
+ (reg_or_const_float_1_operand): New.
+ * config/mips/mips.h: Update Comments.
+ (mips_arg): Add reg_or_const_float_1_operand.
+ * config/mips/mips.md (divdf3); Convert to expander.
+ (divsf3): Ditto.
+ (*divdf3): New pattern.
+ (*divsf3): Ditto.
+
Thu Sep 4 10:43:24 CEST 2003 Jan Hubicka <jh@suse.cz>
* toplev.c (wrapup_global_declarations): Fix final pass in
@@ -91,7 +103,7 @@ Thu Sep 4 10:43:24 CEST 2003 Jan Hubicka <jh@suse.cz>
EXPAND_BUILTIN_SAVEREGS, SETUP_INCOMING_VARARGS,
STRICT_ARGUMENT_NAMING, PRETEND_OUTGOING_VARARGS_NAMED): Convert
to hooks.
-
+
* config/alpha/alpha.c (alpha_output_mi_thunk_osf): Pass function
to aggregate_value_p.
* config/arm/arm.c (arm_init_cumulative_args,
@@ -108,7 +120,7 @@ Thu Sep 4 10:43:24 CEST 2003 Jan Hubicka <jh@suse.cz>
function to aggregate_value_p.
* objc/objc-act.c (generate_struct_by_value_array): Pass NULL to
aggregate_value_p.
-
+
* config/sh/sh-protos.h (sh_builtin_saveregs): Remove.
(sh_attr_renesas_p, sh_cfun_attr_renesas_p, sh_function_arg,
sh_function_arg_advance, sh_pass_in_reg_p): New. * config/sh/sh.c
@@ -150,7 +162,7 @@ Thu Sep 4 10:43:24 CEST 2003 Jan Hubicka <jh@suse.cz>
SETUP_INCOMING_VARARGS, EXPAND_BUILTIN_SAVEREGS,
PROMOTE_PROTOTYPES): Moved to sh.c. * config/sh/sh.md (call): Set
call cookie to indicate renesas calls.
-
+
2003-09-03 Mostafa Hagog <mustafa@il.ibm.com>
* gcse.c (replace_one_set): New function.
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 7fa4ad80ebd..8bd2139d9ef 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -1303,6 +1303,28 @@ reg_or_0_operand (rtx op, enum machine_mode mode)
}
}
+/* Accept a register or the floating point constant 1 in the appropriate mode. */
+
+int
+reg_or_const_float_1_operand (rtx op, enum machine_mode mode)
+{
+ REAL_VALUE_TYPE d;
+
+ switch (GET_CODE (op))
+ {
+ case CONST_DOUBLE:
+ if (mode != GET_MODE (op)
+ || (mode != DFmode && mode != SFmode))
+ return 0;
+
+ REAL_VALUE_FROM_CONST_DOUBLE (d, op);
+ return REAL_VALUES_EQUAL (d, dconst1);
+
+ default:
+ return register_operand (op, mode);
+ }
+}
+
/* Accept the floating point constant 1 in the appropriate mode. */
int
@@ -6714,7 +6736,7 @@ mips_expand_prologue (void)
/* If struct value address is treated as the first argument, make it so. */
if (aggregate_value_p (DECL_RESULT (fndecl), fndecl)
&& ! current_function_returns_pcc_struct
- && struct_value_incoming_rtx == 0)
+ && targetm.calls.struct_value_rtx (fndecl, 0) == 0)
{
tree type = build_pointer_type (fntype);
tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 716c2774beb..b72399ee02c 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -515,9 +515,9 @@ extern const struct mips_cpu_info *mips_tune_info;
N_("Use GP relative sdata/sbss sections (now ignored)")}, \
{"gpopt", 0, \
N_("Use GP relative sdata/sbss sections (now ignored)")}, \
- {"no-gpOPT", 0, \
+ {"no-gpOPT", 0, \
N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
- {"no-gpopt", 0, \
+ {"no-gpopt", 0, \
N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
{"stats", 0, \
N_("Output compiler statistics (now ignored)")}, \
@@ -1415,12 +1415,7 @@ extern const struct mips_cpu_info *mips_tune_info;
on the full register even if a narrower mode is specified. */
#define WORD_REGISTER_OPERATIONS
-/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
- will either zero-extend or sign-extend. The value of this macro should
- be the code that says which one of the two operations is implicitly
- done, NIL if none.
-
- When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
+/* When in 64 bit mode, move insns will sign extend SImode and CCmode
moves. All other references are zero extended. */
#define LOAD_EXTEND_OP(MODE) \
(TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
@@ -1809,31 +1804,31 @@ enum reg_class
sub-initializer must be suitable as an initializer for the type
`HARD_REG_SET' which is defined in `hard-reg-set.h'. */
-#define REG_CLASS_CONTENTS \
-{ \
+#define REG_CLASS_CONTENTS \
+{ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
{ 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
{ 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
{ 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
{ 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
{ 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
- { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
+ { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
{ 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
{ 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
{ 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
{ 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
{ 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
- { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
- { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
+ { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
{ 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
{ 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
- { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
- { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
- { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
- { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
- { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
+ { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
+ { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
+ { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
+ { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
+ { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
{ 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
{ 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
}
@@ -2668,9 +2663,7 @@ typedef struct mips_args {
/* Specify the machine mode that this machine uses
for the index in the tablejump instruction.
- ??? Using HImode in mips16 mode can cause overflow. However, the
- overflow is no more likely than the overflow in a branch
- instruction. Large functions can currently break in both ways. */
+ ??? Using HImode in mips16 mode can cause overflow. */
#define CASE_VECTOR_MODE \
(TARGET_MIPS16 ? HImode : ptr_mode)
@@ -2808,6 +2801,7 @@ typedef struct mips_args {
{"small_int", { CONST_INT }}, \
{"mips_const_double_ok", { CONST_DOUBLE }}, \
{"const_float_1_operand", { CONST_DOUBLE }}, \
+ {"reg_or_const_float_1_operand", { CONST_DOUBLE, REG}}, \
{"simple_memory_operand", { MEM, SUBREG }}, \
{"equality_op", { EQ, NE }}, \
{"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
@@ -3366,7 +3360,7 @@ do { \
do { \
if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
function_section (current_function_decl); \
- (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
+ (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
} while (0)
/* This is how to output an assembler line
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index e843d53734c..7b5f1b7433c 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -2365,6 +2365,17 @@
;; ....................
;;
+(define_expand "divdf3"
+ [(set (match_operand:DF 0 "register_operand" "")
+ (div:DF (match_operand:DF 1 "reg_or_const_float_1_operand" "")
+ (match_operand:DF 2 "register_operand" "")))]
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+{
+ if (const_float_1_operand (operands[1], DFmode))
+ if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
+ FAIL;
+})
+
;; This pattern works around the early SB-1 rev2 core "F1" erratum:
;;
;; If an mfc1 or dmfc1 happens to access the floating point register
@@ -2376,7 +2387,8 @@
;;
;; The workaround is to insert an unconditional 'mov' from/to the
;; long latency op destination register.
-(define_insn "divdf3"
+
+(define_insn "*divdf3"
[(set (match_operand:DF 0 "register_operand" "=f")
(div:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))]
@@ -2395,6 +2407,17 @@
(const_int 4)))])
+(define_expand "divsf3"
+ [(set (match_operand:SF 0 "register_operand" "")
+ (div:SF (match_operand:SF 1 "reg_or_const_float_1_operand" "")
+ (match_operand:SF 2 "register_operand" "")))]
+ "TARGET_HARD_FLOAT"
+{
+ if (const_float_1_operand (operands[1], SFmode))
+ if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
+ FAIL;
+})
+
;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
;; "divdf3" comment for details).
;;
@@ -2406,7 +2429,7 @@
;; Therefore, we only allow div.s if not working around SB-1 rev2
;; errata, or if working around those errata and a slight loss of
;; precision is OK (i.e., flag_unsafe_math_optimizations is set).
-(define_insn "divsf3"
+(define_insn "*divsf3"
[(set (match_operand:SF 0 "register_operand" "=f")
(div:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
--
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