* config/mips/mips.h (PROCESSOR_R9000): New processor_type.

	(TARGET_MIPS9000, TUNE_MIPS9000): New macros.
	(GENERATE_MULT3_SI): True for TARGET_MIPS9000.
	* config/mips/mips.c (mips_cpu_info_table): Add rm9000 entry.
	(mips_rtx_costs): Adjust integer multiplication costs for the rm9000.
	(mips_issue_rate): Handle PROCESSOR_R9000.
	(mips_use_dfa_pipeline_interface): Likewise.
	* config/mips/9000.md: New file.
	* config/mips/mips.md: Include it.
	(define_attr cpu): Add r9000.
	(mulsi3_mult3): Use "mul" for rm9000 code.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@69397 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog

+2003-07-15  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/mips/mips.h (PROCESSOR_R9000): New processor_type.
+	(TARGET_MIPS9000, TUNE_MIPS9000): New macros.
+	(GENERATE_MULT3_SI): True for TARGET_MIPS9000.
+	* config/mips/mips.c (mips_cpu_info_table): Add rm9000 entry.
+	(mips_rtx_costs): Adjust integer multiplication costs for the rm9000.
+	(mips_issue_rate): Handle PROCESSOR_R9000.
+	(mips_use_dfa_pipeline_interface): Likewise.
+	* config/mips/9000.md: New file.
+	* config/mips/mips.md: Include it.
+	(define_attr cpu): Add r9000.
+	(mulsi3_mult3): Use "mul" for rm9000 code.
+
 2003-07-15  Stan Cox  <scox@redhat.com>
 	* config/mips/mips.h (PROCESSOR_R7000): New processor_type.

gcc/config/mips/9000.md

+;; DFA-based pipeline description for the RM9000.
+;;   Copyright (C) 2003 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 2, or (at your
+;; option) any later version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING.  If not, write to the
+;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
+;; MA 02111-1307, USA.
+
+(define_automaton "rm9k_main, rm9k_imul, rm9k_fdiv")
+
+;; These units are for insns that can issue in either pipe.  We don't
+;; want to use constructs like "rm9k_m | rm9k_f_int" since that would
+;; needlessly make an insn prefer the M pipe.
+(define_cpu_unit "rm9k_any1" "rm9k_main")
+(define_cpu_unit "rm9k_any2" "rm9k_main")
+
+;; F and M pipe units, for instructions that must be issued by a
+;; particular pipe.  Split the F pipe into two units so that integer
+;; instructions can issue while the FPU is busy.  We don't need to
+;; split M because it is only ever reserved for a single cycle.
+(define_cpu_unit "rm9k_m" "rm9k_main")
+(define_cpu_unit "rm9k_f_int" "rm9k_main")
+(define_cpu_unit "rm9k_f_float" "rm9k_main")
+
+(exclusion_set "rm9k_f_int" "rm9k_f_float")
+
+;; Multiply/divide units.
+(define_cpu_unit "rm9k_imul" "rm9k_imul")
+(define_cpu_unit "rm9k_fdiv" "rm9k_fdiv")
+
+(define_insn_reservation "rm9k_load" 3
+  (and (eq_attr "cpu" "r9000")
+       (eq_attr "type" "load"))
+  "rm9k_m")
+
+(define_insn_reservation "rm9k_store" 1
+  (and (eq_attr "cpu" "r9000")
+       (eq_attr "type" "store"))
+  "rm9k_m")
+
+(define_insn_reservation "rm9k_int" 1
+  (and (eq_attr "cpu" "r9000")
+       (eq_attr "type" "move,arith,darith,const,icmp,nop"))
+  "rm9k_any1 | rm9k_any2")
+
+(define_insn_reservation "rm9k_int_cmove" 2
+  (and (eq_attr "cpu" "r9000")
+       (and (eq_attr "type" "condmove")
+	    (eq_attr "mode" "SI,DI")))
+  "rm9k_any1 | rm9k_any2")
+
+;; This applies to both 'mul' and 'mult'.
+(define_insn_reservation "rm9k_mulsi" 3
+  (and (eq_attr "cpu" "r9000")
+       (and (eq_attr "type" "imul,imadd")
+	    (eq_attr "mode" "!DI")))
+  "rm9k_f_int")
+
+(define_insn_reservation "rm9k_muldi" 7
+  (and (eq_attr "cpu" "r9000")
+       (and (eq_attr "type" "imul,imadd")
+	    (eq_attr "mode" "DI")))
+  "rm9k_f_int + rm9k_imul * 7")
+
+(define_insn_reservation "rm9k_divsi" 38
+  (and (eq_attr "cpu" "r9000")
+       (and (eq_attr "type" "idiv")
+	    (eq_attr "mode" "!DI")))
+  "rm9k_f_int + rm9k_imul * 38")
+
+(define_insn_reservation "rm9k_divdi" 70
+  (and (eq_attr "cpu" "r9000")
+       (and (eq_attr "type" "idiv")
+	    (eq_attr "mode" "DI")))
+  "rm9k_f_int + rm9k_imul * 70")
+
+(define_insn_reservation "rm9k_mfhilo" 1
+  (and (eq_attr "cpu" "r9000")
+       (and (eq_attr "type" "hilo")
+	    (not (match_operand 0 "hilo_operand" ""))))
+  "rm9k_f_int")
+
+(define_insn_reservation "rm9k_mthilo" 5
+  (and (eq_attr "cpu" "r9000")
+       (and (eq_attr "type" "hilo")
+	    (match_operand 0 "hilo_operand" "")))
+  "rm9k_f_int")
+
+(define_insn_reservation "rm9k_xfer" 2
+  (and (eq_attr "cpu" "r9000")
+       (eq_attr "type" "xfer"))
+  "rm9k_m")
+
+(define_insn_reservation "rm9k_fquick" 2
+  (and (eq_attr "cpu" "r9000")
+       (eq_attr "type" "fabs,fneg,fcmp"))
+  "rm9k_f_float")
+
+(define_insn_reservation "rm9k_fcmove" 2
+  (and (eq_attr "cpu" "r9000")
+       (and (eq_attr "type" "condmove")
+	    (eq_attr "mode" "SF,DF")))
+  "rm9k_m")
+
+(define_insn_reservation "rm9k_fadd" 6
+  (and (eq_attr "cpu" "r9000")
+       (eq_attr "type" "fadd,fcvt"))
+  "rm9k_f_float")
+
+(define_insn_reservation "rm9k_fmuls" 6
+  (and (eq_attr "cpu" "r9000")
+       (and (eq_attr "type" "fmul,fmadd")
+	    (eq_attr "mode" "SF")))
+  "rm9k_f_float")
+
+(define_insn_reservation "rm9k_fmuld" 9
+  (and (eq_attr "cpu" "r9000")
+       (and (eq_attr "type" "fmul,fmadd")
+	    (eq_attr "mode" "DF")))
+  "rm9k_f_float * 3")
+
+(define_insn_reservation "rm9k_fdivs" 22
+  (and (eq_attr "cpu" "r9000")
+       (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
+	    (eq_attr "mode" "SF")))
+  "rm9k_f_float + rm9k_fdiv * 22")
+
+(define_insn_reservation "rm9k_fdivd" 37
+  (and (eq_attr "cpu" "r9000")
+       (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
+	    (eq_attr "mode" "DF")))
+  "rm9k_f_float + rm9k_fdiv * 37")
+
+(define_insn_reservation "rm9k_branch" 2
+  (and (eq_attr "cpu" "r9000")
+       (eq_attr "type" "branch,jump,call"))
+  "rm9k_any1 | rm9k_any2")
+
+(define_insn_reservation "rm9k_unknown" 1
+  (and (eq_attr "cpu" "r9000")
+       (eq_attr "type" "unknown,multi"))
+  "rm9k_m + rm9k_f_int + rm9k_any1 + rm9k_any2")

gcc/config/mips/mips.c

@@ -808,6 +808,7 @@ const struct mips_cpu_info mips_cpu_info_table[] = {
   { "vr5400", PROCESSOR_R5400, 4 },
   { "vr5500", PROCESSOR_R5500, 4 },
   { "rm7000", PROCESSOR_R7000, 4 },
+  { "rm9000", PROCESSOR_R9000, 4 },
 
   /* MIPS32 */
   { "4kc", PROCESSOR_4KC, 32 },
@@ -2664,6 +2665,8 @@ mips_rtx_costs (x, code, outer_code, total)
         *total = COSTS_N_INSNS ((mode == DImode) ? 4 : 3);
       else if (TUNE_MIPS7000)
         *total = COSTS_N_INSNS (mode == DImode ? 9 : 5);
+      else if (TUNE_MIPS9000)
+        *total = COSTS_N_INSNS (mode == DImode ? 8 : 3);
       else if (TUNE_MIPS6000)
         *total = COSTS_N_INSNS (17);
       else if (TUNE_MIPS5000)
@@ -10265,6 +10268,7 @@ mips_issue_rate ()
     case PROCESSOR_R5400: return 2;
     case PROCESSOR_R5500: return 2;
     case PROCESSOR_R7000: return 2;
+    case PROCESSOR_R9000: return 2;
 
     default:
       return 1;
@@ -10285,6 +10289,7 @@ mips_use_dfa_pipeline_interface ()
     case PROCESSOR_R5400:
     case PROCESSOR_R5500:
     case PROCESSOR_R7000:
+    case PROCESSOR_R9000:
     case PROCESSOR_SR71000:
       return true;
 

gcc/config/mips/mips.h

@@ -67,6 +67,7 @@ enum processor_type {
   PROCESSOR_R5500,
   PROCESSOR_R7000,
   PROCESSOR_R8000,
+  PROCESSOR_R9000,
   PROCESSOR_SB1,
   PROCESSOR_SR71000
 };
@@ -331,6 +332,7 @@ extern const struct mips_cpu_info *mips_tune_info;
 #define TARGET_MIPS5400             (mips_arch == PROCESSOR_R5400)
 #define TARGET_MIPS5500             (mips_arch == PROCESSOR_R5500)
 #define TARGET_MIPS7000             (mips_arch == PROCESSOR_R7000)
+#define TARGET_MIPS9000             (mips_arch == PROCESSOR_R9000)
 #define TARGET_SB1                  (mips_arch == PROCESSOR_SB1)
 #define TARGET_SR71K                (mips_arch == PROCESSOR_SR71000)
 
@@ -343,6 +345,7 @@ extern const struct mips_cpu_info *mips_tune_info;
 #define TUNE_MIPS5500               (mips_tune == PROCESSOR_R5500)
 #define TUNE_MIPS6000               (mips_tune == PROCESSOR_R6000)
 #define TUNE_MIPS7000               (mips_tune == PROCESSOR_R7000)
+#define TUNE_MIPS9000               (mips_tune == PROCESSOR_R9000)
 #define TUNE_SB1                    (mips_tune == PROCESSOR_SB1)
 #define TUNE_SR71K                  (mips_tune == PROCESSOR_SR71000)
 
@@ -766,6 +769,7 @@ extern const struct mips_cpu_info *mips_tune_info;
                                   || TARGET_MIPS5400                    \
                                   || TARGET_MIPS5500                    \
                                   || TARGET_MIPS7000                    \
+                                  || TARGET_MIPS9000                    \
                                   || ISA_MIPS32	                        \
                                   || ISA_MIPS32R2                       \
                                   || ISA_MIPS64)                        \

gcc/config/mips/mips.md

@@ -195,7 +195,7 @@
 
 ;; ??? Fix everything that tests this attribute.
 (define_attr "cpu"
-  "default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,sb1,sr71000"
+  "default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000"
   (const (symbol_ref "mips_cpu_attr")))
 
 ;; The type of hardware hazard associated with this instruction.
@@ -624,6 +624,7 @@
 (include "5400.md")
 (include "5500.md")
 (include "7000.md")
+(include "9000.md")
 (include "sr71k.md")
 
 
@@ -1498,6 +1499,7 @@
       || TARGET_MIPS5400
       || TARGET_MIPS5500
       || TARGET_MIPS7000
+      || TARGET_MIPS9000
       || ISA_MIPS32
       || ISA_MIPS32R2
       || ISA_MIPS64)