Skip to content

GitLab

Commit 76a5df9b authored by William Bryan's avatar William Bryan Committed by Fadi Kassem
Browse files

Core data initialization and 24-core support 

RTC: 140187
RTC: 140186
Change-Id: I574acdc3933b4bc181a584226ea432b9abe72592
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22182

Reviewed-by: default avatarWael Elessawy <welessa@us.ibm.com>
Tested-by: default avatarFadi Kassem <fmkassem@us.ibm.com>
Reviewed-by: default avatarFadi Kassem <fmkassem@us.ibm.com>
parent e71f5784
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 288 additions and 556 deletions
.gitignore
View file @ 76a5df9b
......@@ -16,3 +16,5 @@ env.bash
src/build/
*.sw*
obj/
*~
*.save*
src/ipc_func_ids.h
View file @ 76a5df9b
......@@ -60,6 +60,9 @@ IPC_FUNCIDS_TABLE_START
IPC_FUNC_ID(IPC_ST_APSS_START_PWR_MEAS_READ_FUNCID)
IPC_FUNC_ID(IPC_ST_APSS_CONTINUE_PWR_MEAS_READ_FUNCID)
IPC_FUNC_ID(IPC_ST_APSS_COMPLETE_PWR_MEAS_READ_FUNCID)
IPC_FUNC_ID(IPC_ST_SCOM_OPERATION)
IPC_FUNC_ID(IPC_ST_CORE_DATA_LOW_FUNCID)
IPC_FUNC_ID(IPC_ST_CORE_DATA_HIGH_FUNCID)
IPC_FUNCIDS_ST_END(OCCHW_INST_ID_GPE0)
//Functions that are only supported by GPE1 should be defined here
......
src/lib/occlib/liboccfiles.mk
View file @ 76a5df9b
......@@ -42,6 +42,7 @@
##########################################################################
C-SOURCES = \
core_data.c \
ipc_core.c \
ipc_init.c \
ipc_msgq.c \
......
src/occ_405/amec/amec_smh.h
View file @ 76a5df9b
......@@ -60,7 +60,8 @@
// Number of uS in 1 RTL tick (250=250us)
#define AMEC_US_PER_TICK MICS_PER_TICK
// Number of uS in 1 full period of the AMEC State Machine (2000=2mS, 8 RTL ticks)
// Number of uS in 1 full period of the AMEC State Machine
// We cycle through the 8 states twice per tick cycle (16 ticks), so 8 * 250us = 2ms
#define AMEC_US_PER_SMH_PERIOD (AMEC_SMH_STATES_PER_LVL * MICS_PER_TICK)
// Number of <AMEC_US_PER_SMH_PERIOD> that happen in 1 second
#define AMEC_SMH_PERIODS_IN_1SEC (10000000 / AMEC_US_PER_SMH_PERIOD)
......
src/occ_405/cmdh/cmdh_fsp.c
View file @ 76a5df9b
......@@ -1263,6 +1263,8 @@ errlHndl_t cmdh_processTmgtRequest (const cmdh_fsp_cmd_t * i_cmd_ptr,
i_rsp_ptr->data_length[1] = 0;
i_rsp_ptr->rc = ERRL_RC_SUCCESS;
CMDH_TRAC_INFO("cmdh_processTmgtRequest: Received command type 0x%02X", l_cmd_type);
// Run command function based on cmd_type
switch(l_cmd_type)
{
......
src/occ_405/incl/common_types.h
View file @ 76a5df9b
......@@ -27,7 +27,7 @@
#define _COMMON_TYPES_H
#include <stdint.h>
#include <core_data.h>
#ifdef USE_SSX_APP_CFG_H
#include <ssx_app_cfg.h>
#endif
......@@ -125,6 +125,22 @@ struct image_header
typedef struct image_header imageHdr_t;
typedef struct ipc_scom_op
{
uint32_t addr; // Register address
uint64_t data; // Data for read/write
uint32_t size; // Size of data buffer
uint8_t read; // Read (1) or write (0)
int rc; // Error of SCOM operation
} ipc_scom_op_t;
typedef struct ipc_core_data_parms
{
CoreData* data;
uint32_t core_num;
uint32_t rc;
} ipc_core_data_parms_t;
extern uint32_t __READ_ONLY_DATA_LEN__;
extern uint32_t __WRITEABLE_DATA_ADDR__;
extern uint32_t __WRITEABLE_DATA_LEN__;
......
src/occ_405/main.c
View file @ 76a5df9b
......@@ -1000,8 +1000,7 @@ void Main_thread_routine(void *private)
//Initialize structures for collecting core data.
//It needs to run before RTLoop start as pore initialization needs to be
// done before task to collect core data starts.
// TEMP -- NOT NEEDED IN PHASE1
// proc_core_init();
proc_core_init();
CHECKPOINT(PROC_CORE_INITIALIZED);
// Run slave OCC init on all OCCs. Master-only initialization will be
......
src/occ_405/occLinkInputFile
View file @ 76a5df9b
......@@ -48,6 +48,7 @@ INPUT ( amec_data.o
ppc405_lib_core.o
ppc405_mmu_asm.o
ppc405_thread_init.o
proc_data.o
proc_pstate.o
reset.o
rtls_tables.o
......
src/occ_405/occ_service_codes.h
View file @ 76a5df9b
......@@ -125,9 +125,8 @@ enum occExtReasonCode
ERC_CALLER_SEM_POSTING_FAILURE = 0x0000000d,
ERC_CREATE_SEM_FAILURE = 0x0000000e,
ERC_LOW_CORE_PORE_FLEX_CREATE_FAILURE = 0x0000000f,
ERC_HIGH_CORE_PORE_FLEX_CREATE_FAILURE = 0x00000010,
ERC_FAST_CORE_PORE_FLEX_CREATE_FAILURE = 0x00000011,
ERC_LOW_CORE_GPE_REQUEST_CREATE_FAILURE = 0x0000000f,
ERC_HIGH_CORE_GPE_REQUEST_CREATE_FAILURE = 0x00000010,
ERC_SSX_IRQ_SETUP_FAILURE = 0x00000012,
ERC_SSX_IRQ_HANDLER_SET_FAILURE = 0x00000013,
......
src/occ_405/proc/proc_data.c
View file @ 76a5df9b
This diff is collapsed.
src/occ_405/proc/proc_data.h
View file @ 76a5df9b
......@@ -29,7 +29,7 @@
#include <occ_common.h>
#include <ssx.h>
#include "rtls.h"
//#include "gpe_data.h"
#include "core_data.h"
//Returns 0 if the specified core is not present. Otherwise, returns none-zero.
#define CORE_PRESENT(occ_core_id) \
......@@ -38,35 +38,35 @@
//Takes an OCC core id and converts it to a core id that
//can be used by the hardware. The caller needs to send in
//a valid core id. Since type is uchar so there is no need to check for
//case less than 0. If core id is invalid then returns unconfigured core 16.
//case less than 0. If core id is invalid then returns unconfigured core 24.
#define CORE_OCC2HW(occ_core_id) \
((occ_core_id <= 15) ? G_occ2hw_core_id[occ_core_id] : 16)
((occ_core_id <= 23) ? G_occ2hw_core_id[occ_core_id] : 24)
//Takes a hardware core id and returns a OCC core id.
//The caller needs to send in a valid core id. Since type is uchar so
//there is no need to check for case less than 0. If core id
//is invalid then returns unconfigured core 16.
//is invalid then returns unconfigured core 24.
#define CORE_HW2OCC(hw_core_id) \
((hw_core_id <= 15) ? G_hw2occ_core_id[hw_core_id] : 16)
((hw_core_id <= 23) ? G_hw2occ_core_id[hw_core_id] : 24)
#define ALL_CORES_MASK 0xffff0000
#define ALL_CORES_MASK 0xffffff00
#define CORE0_PRESENT_MASK 0x80000000ul
#define CORE0_PRESENT_MASK_GPE 0x8000000000000000ull
#define MAX_NUM_HW_CORES 16
#define MAX_NUM_FW_CORES 12
#define MAX_NUM_HW_CORES 24
#define MAX_NUM_FW_CORES 24
#define THREADS_PER_CORE 8
#define MAX_MEM_PARTS 4
#define CORE_MID_POINT (MAX_NUM_FW_CORES / 2)
#define THREADS_PER_CORE 4
#define NUM_FAST_CORE_DATA_BUFF 2
#define NUM_CORE_DATA_BUFF 7
#define NUM_CORE_DATA_DOUBLE_BUF 2
#define NUM_CORE_DATA_EMPTY_BUF 1
#define LO_CORES_MASK 0x7e000000
#define HI_CORES_MASK 0x007e0000
#define HW_CORES_MASK 0xffff0000
#define LO_CORES_MASK 0xfff00000
#define HI_CORES_MASK 0x000fff00
#define HW_CORES_MASK 0xffffff00
enum eOccProcCores
{
......@@ -82,44 +82,35 @@ enum eOccProcCores
CORE_9 = 9,
CORE_10 = 10,
CORE_11 = 11,
CORE_12 = 12,
CORE_13 = 13,
CORE_14 = 14,
CORE_15 = 15,
CORE_16 = 16,
CORE_17 = 17,
CORE_18 = 18,
CORE_19 = 19,
CORE_20 = 20,
CORE_21 = 21,
CORE_22 = 22,
CORE_23 = 23,
};
// TEMP -- CoreData no longer exists
//typedef CoreData gpe_bulk_core_data_t;
//Processor data collect structures used for task data pointers
//gpe_req.request.parameter points to GpeGetCoreDataParms
// TEMP -- CoreData / PoreFlex objects no longer exist
/*
struct bulk_core_data_task {
uint8_t start_core;
uint8_t current_core;
uint8_t end_core;
gpe_bulk_core_data_t * core_data_ptr;
PoreFlex gpe_req;
CoreData * core_data_ptr;
GpeRequest gpe_req;
} __attribute__ ((__packed__));
typedef struct bulk_core_data_task bulk_core_data_task_t;
*/
//Only PCBS_LOCAL_PSTATE_FREQ_TARGET_STATUS_REG register is being
//collected at this time. Other register will be added when needed.
struct fast_core_data {
uint64_t pcbs_lpstate_freq_target_sr;
} __attribute__ ((__packed__));
typedef struct fast_core_data fast_core_data_t;
//gpe fast core data structure
struct gpe_fast_core_data {
uint32_t tod;
uint32_t reserved;
fast_core_data_t core_data[MAX_NUM_HW_CORES];
} __attribute__ ((__packed__));
typedef struct gpe_fast_core_data gpe_fast_core_data_t;
//Global low and high cores structures used for task data pointers
// TEMP -- CoreData / PoreFlex objects no longer exist
//extern bulk_core_data_task_t G_low_cores;
//extern bulk_core_data_task_t G_high_cores;
extern bulk_core_data_task_t G_low_cores;
extern bulk_core_data_task_t G_high_cores;
//Global G_present_cores is bitmask of all OCC core numbering
extern uint32_t G_present_cores;
......@@ -151,20 +142,6 @@ extern uint32_t G_empath_error_core_mask;
#define CORE_EMPATH_ERROR(occ_core_id) \
((CORE0_PRESENT_MASK >> occ_core_id) & G_empath_error_core_mask)
//Takes an OCC core id and converts it to a core id that
//can be used by the hardware. The caller needs to send in
//a valid core id. Since type is uchar so there is no need to check for
//case less than 0. If core id is invalid then returns unconfigured core 16.
#define CORE_OCC2HW(occ_core_id) \
((occ_core_id <= 15) ? G_occ2hw_core_id[occ_core_id] : 16)
//Takes a hardware core id and returns a OCC core id.
//The caller needs to send in a valid core id. Since type is uchar so
//there is no need to check for case less than 0. If core id
//is invalid then returns unconfigured core 16.
#define CORE_HW2OCC(hw_core_id) \
((hw_core_id <= 15) ? G_hw2occ_core_id[hw_core_id] : 16)
//Collect bulk core data for all cores in specified range
void task_core_data( task_t * i_task );
......@@ -176,11 +153,6 @@ void task_fast_core_data( task_t * i_task );
//Returns a pointer to the most up-to-date bulk core data for the core
//associated with the specified OCC core id.
// TEMP -- CoreData / PoreFlex objects no longer exist
//gpe_bulk_core_data_t * proc_get_bulk_core_data_ptr( const uint8_t i_occ_core_id );
//Returns a pointer to the most up-to-date fast core data
// TEMP -- CoreData / PoreFlex objects no longer exist
//gpe_fast_core_data_t * proc_get_fast_core_data_ptr( void );
CoreData * proc_get_bulk_core_data_ptr( const uint8_t i_occ_core_id );
#endif //_PROC_DATA_H
src/occ_405/proc/proc_data_control.c
View file @ 76a5df9b
......@@ -24,7 +24,7 @@
/* IBM_PROLOG_END_TAG */
#include "proc_data.h"
#include "pgp_async.h"
#include "occhw_async.h"
#include "threadSch.h"
#include "pmc_register_addresses.h"
#include "proc_data_service_codes.h"
......@@ -34,7 +34,6 @@
#include "rtls.h"
#include "apss.h"
#include "state.h"
#include "gpe_control.h"
#include "occ_sys_config.h"
// Pore flex request for GPE job. The initialization will be done one time
......@@ -141,8 +140,8 @@ void proc_core_data_control_init( void )
do
{
//FIXME: Need to move this object to the PGPE (later phase)
//Initializes PoreFlex object for fast core data
//FIXME: Need to change this to use PGPE queue
//Initializes PoreFlex object for pstate control
rc = pore_flex_create( &G_core_data_control_req, //gpe_req for the task
&G_pore_gpe0_queue, //queue
gpe_set_pstates, //entry point
......@@ -192,6 +191,8 @@ void proc_core_data_control_init( void )
// End Function Specification
void task_core_data_control( task_t * i_task )
{
//TEMP/TODO: proc_core_data_control_init needs to be called from proc_core_init()
// when this task is enabled for it to function properly.
errlHndl_t l_err = NULL; //Error handler
tracDesc_t l_trace = NULL; //Temporary trace descriptor
int rc = 0; //Return code
......
src/occ_405/rtls/rtls.h
View file @ 76a5df9b
......@@ -41,9 +41,9 @@ typedef struct task {
// These are used as indices into the task table defined below.
typedef enum {
TASK_ID_APSS_START = 0x00,
// TASK_ID_CORE_DATA_LOW,
TASK_ID_CORE_DATA_LOW,
TASK_ID_APSS_CONT,
// TASK_ID_CORE_DATA_HIGH,
TASK_ID_CORE_DATA_HIGH,
TASK_ID_APSS_DONE,
// TASK_ID_DCOM_RX_INBX,
// TASK_ID_DCOM_TX_INBX,
......
src/occ_405/rtls/rtls_tables.c
View file @ 76a5df9b
......@@ -95,11 +95,9 @@
task_t G_task_table[TASK_END] = {
// flags, func_ptr, data_ptr,// task_id_t
{ FLAGS_APSS_START_MEAS, task_apss_start_pwr_meas, NULL }, // TASK_ID_APSS_START
// TEMP -- PORE ISSUES
// { FLAGS_LOW_CORES_DATA, task_core_data, (void *) &G_low_cores},
{ FLAGS_LOW_CORES_DATA, task_core_data, (void *) &G_low_cores},
{ FLAGS_APSS_CONT_MEAS, task_apss_continue_pwr_meas, NULL }, // TASK_ID_APSS_CONT
// TEMP -- PORE ISSUES
// { FLAGS_HIGH_CORES_DATA, task_core_data, (void *) &G_high_cores},
{ FLAGS_HIGH_CORES_DATA, task_core_data, (void *) &G_high_cores},
{ FLAGS_APSS_DONE_MEAS, task_apss_complete_pwr_meas, NULL }, // TASK_ID_APSS_DONE
// TEMP -- NOT SUPPORTED YET IN PHASE1
// { FLAGS_DCOM_RX_SLV_INBX, task_dcom_rx_slv_inbox, NULL }, // TASK_ID_DCOM_RX_INBX
......@@ -131,10 +129,10 @@ task_t G_task_table[TASK_END] = {
const uint8_t G_tick0_seq[] = {
TASK_ID_APSS_START,
//TASK_ID_CORE_DATA_LOW,
TASK_ID_CORE_DATA_LOW,
//TASK_ID_DIMM_SM,
TASK_ID_APSS_CONT,
//TASK_ID_CORE_DATA_HIGH,
TASK_ID_CORE_DATA_HIGH,
TASK_ID_APSS_DONE,
//TASK_ID_CORE_DATA_CONTROL,
//TASK_ID_DCOM_WAIT_4_MSTR,
......@@ -151,7 +149,7 @@ const uint8_t G_tick0_seq[] = {
const uint8_t G_tick1_seq[] = {
TASK_ID_APSS_START,
//TASK_ID_CORE_DATA_LOW,
TASK_ID_CORE_DATA_LOW,
//TASK_ID_GPU_SM,
TASK_ID_APSS_CONT,
TASK_ID_APSS_DONE,
......@@ -170,10 +168,10 @@ const uint8_t G_tick1_seq[] = {
const uint8_t G_tick2_seq[] = {
TASK_ID_APSS_START,
//TASK_ID_CORE_DATA_LOW,
TASK_ID_CORE_DATA_LOW,
//TASK_ID_DIMM_SM,
TASK_ID_APSS_CONT,
//TASK_ID_CORE_DATA_HIGH,
TASK_ID_CORE_DATA_HIGH,
TASK_ID_APSS_DONE,
//TASK_ID_CORE_DATA_CONTROL,
//TASK_ID_DCOM_WAIT_4_MSTR,
......@@ -191,7 +189,7 @@ const uint8_t G_tick3_seq[] = {
TASK_ID_APSS_START,
//TASK_ID_GPU_SM,
TASK_ID_APSS_CONT,
//TASK_ID_CORE_DATA_HIGH,
TASK_ID_CORE_DATA_HIGH,
TASK_ID_APSS_DONE,
//TASK_ID_MEM_DEADMAN,
//TASK_ID_CORE_DATA_CONTROL,
......@@ -208,10 +206,10 @@ const uint8_t G_tick3_seq[] = {
const uint8_t G_tick4_seq[] = {
TASK_ID_APSS_START,
//TASK_ID_CORE_DATA_LOW,
TASK_ID_CORE_DATA_LOW,
//TASK_ID_DIMM_SM,
TASK_ID_APSS_CONT,
//TASK_ID_CORE_DATA_HIGH,
TASK_ID_CORE_DATA_HIGH,
TASK_ID_APSS_DONE,
//TASK_ID_CORE_DATA_CONTROL,
//TASK_ID_DCOM_WAIT_4_MSTR,
......@@ -228,7 +226,7 @@ const uint8_t G_tick4_seq[] = {
const uint8_t G_tick5_seq[] = {
TASK_ID_APSS_START,
//TASK_ID_CORE_DATA_LOW,
TASK_ID_CORE_DATA_LOW,
//TASK_ID_GPU_SM,
TASK_ID_APSS_CONT,
TASK_ID_APSS_DONE,
......@@ -247,10 +245,10 @@ const uint8_t G_tick5_seq[] = {
const uint8_t G_tick6_seq[] = {
TASK_ID_APSS_START,
//TASK_ID_CORE_DATA_LOW,
TASK_ID_CORE_DATA_LOW,
//TASK_ID_DIMM_SM,
TASK_ID_APSS_CONT,
//TASK_ID_CORE_DATA_HIGH,
TASK_ID_CORE_DATA_HIGH,
TASK_ID_APSS_DONE,
//TASK_ID_CORE_DATA_CONTROL,
//TASK_ID_DCOM_WAIT_4_MSTR,
......@@ -268,7 +266,7 @@ const uint8_t G_tick7_seq[] = {
TASK_ID_APSS_START,
//TASK_ID_GPU_SM,
TASK_ID_APSS_CONT,
//TASK_ID_CORE_DATA_HIGH,
TASK_ID_CORE_DATA_HIGH,
TASK_ID_APSS_DONE,
//TASK_ID_MEM_DEADMAN,
//TASK_ID_CORE_DATA_CONTROL,
......@@ -285,10 +283,10 @@ const uint8_t G_tick7_seq[] = {
const uint8_t G_tick8_seq[] = {
TASK_ID_APSS_START,
//TASK_ID_CORE_DATA_LOW,
TASK_ID_CORE_DATA_LOW,
//TASK_ID_DIMM_SM,
TASK_ID_APSS_CONT,
//TASK_ID_CORE_DATA_HIGH,
TASK_ID_CORE_DATA_HIGH,
TASK_ID_APSS_DONE,
//TASK_ID_CORE_DATA_CONTROL,
//TASK_ID_DCOM_WAIT_4_MSTR,
......@@ -305,7 +303,7 @@ const uint8_t G_tick8_seq[] = {
const uint8_t G_tick9_seq[] = {
TASK_ID_APSS_START,
//TASK_ID_CORE_DATA_LOW,
TASK_ID_CORE_DATA_LOW,
//TASK_ID_GPU_SM,
TASK_ID_APSS_CONT,
TASK_ID_APSS_DONE,
......@@ -324,10 +322,10 @@ const uint8_t G_tick9_seq[] = {
const uint8_t G_tick10_seq[] = {
TASK_ID_APSS_START,
//TASK_ID_CORE_DATA_LOW,
TASK_ID_CORE_DATA_LOW,
//TASK_ID_DIMM_SM,
TASK_ID_APSS_CONT,
//TASK_ID_CORE_DATA_HIGH,
TASK_ID_CORE_DATA_HIGH,
TASK_ID_APSS_DONE,
//TASK_ID_CORE_DATA_CONTROL,
//TASK_ID_DCOM_WAIT_4_MSTR,
......@@ -345,7 +343,7 @@ const uint8_t G_tick11_seq[] = {
TASK_ID_APSS_START,
//TASK_ID_GPU_SM,
TASK_ID_APSS_CONT,
//TASK_ID_CORE_DATA_HIGH,
TASK_ID_CORE_DATA_HIGH,
TASK_ID_APSS_DONE,
//TASK_ID_MEM_DEADMAN,
//TASK_ID_CORE_DATA_CONTROL,
......@@ -362,10 +360,10 @@ const uint8_t G_tick11_seq[] = {
const uint8_t G_tick12_seq[] = {
TASK_ID_APSS_START,
//TASK_ID_CORE_DATA_LOW,
TASK_ID_CORE_DATA_LOW,
//TASK_ID_DIMM_SM,
TASK_ID_APSS_CONT,
//TASK_ID_CORE_DATA_HIGH,
TASK_ID_CORE_DATA_HIGH,
TASK_ID_APSS_DONE,
//TASK_ID_CORE_DATA_CONTROL,
//TASK_ID_DCOM_WAIT_4_MSTR,
......@@ -382,7 +380,7 @@ const uint8_t G_tick12_seq[] = {
const uint8_t G_tick13_seq[] = {
TASK_ID_APSS_START,
//TASK_ID_CORE_DATA_LOW,
TASK_ID_CORE_DATA_LOW,
//TASK_ID_GPU_SM,
TASK_ID_APSS_CONT,
TASK_ID_APSS_DONE,
......@@ -401,10 +399,10 @@ const uint8_t G_tick13_seq[] = {
const uint8_t G_tick14_seq[] = {
TASK_ID_APSS_START,
//TASK_ID_CORE_DATA_LOW,
TASK_ID_CORE_DATA_LOW,
//TASK_ID_DIMM_SM,
TASK_ID_APSS_CONT,
//TASK_ID_CORE_DATA_HIGH,
TASK_ID_CORE_DATA_HIGH,
TASK_ID_APSS_DONE,
//TASK_ID_CORE_DATA_CONTROL,
//TASK_ID_DCOM_WAIT_4_MSTR,
......@@ -422,7 +420,7 @@ const uint8_t G_tick15_seq[] = {
TASK_ID_APSS_START,
//TASK_ID_GPU_SM,
TASK_ID_APSS_CONT,
//TASK_ID_CORE_DATA_HIGH,
TASK_ID_CORE_DATA_HIGH,
TASK_ID_APSS_DONE,
//TASK_ID_MEM_DEADMAN,
//TASK_ID_CORE_DATA_CONTROL,
......
src/occ_405/ssx_app_cfg.h
View file @ 76a5df9b
......@@ -102,6 +102,7 @@ do { \
#define APPCFG_OCC_INSTANCE_ID 4
#define PROC_DEBUG 1
// Common configuration groups for verification. Bypass time-consuming setup
// or setup done by procedures for simulation environments, and set up special
// I/O configurations for simulation environments.
......
src/occ_405/topfiles.mk
View file @ 76a5df9b
......@@ -52,6 +52,7 @@ TOP-C-SOURCES = amec/amec_data.c \
mode.c \
occ_sys_config.c \
occbuildname.c \
proc/proc_data.c \
proc/proc_pstate.c \
pss/apss.c \
reset.c \
......
src/occ_gpe0/apss_util.c
View file @ 76a5df9b
......@@ -170,5 +170,27 @@ void busy_wait(uint32_t t_microseconds)
while (current_decrementer_value > end_decrementer_value) // Wait until end_decrementer_value is reached
MFDEC(current_decrementer_value);
}
void ipc_scom_operation(ipc_msg_t* cmd, void* arg)
{
int l_rc;
ipc_async_cmd_t *async_cmd = (ipc_async_cmd_t*)cmd;
ipc_scom_op_t *scom_op = (ipc_scom_op_t*) async_cmd->cmd_data;
if (scom_op->read)
{
l_rc = getscom_abs(scom_op->addr, &scom_op->data);
}
else
{
l_rc = putscom_abs(scom_op->addr, scom_op->data);
}
if(l_rc)
{
scom_op->rc = l_rc;
PK_TRACE("Error doing generic scom! RC: 0x%08X Addr: 0x%08X Read: %d Data: 0x%08X", l_rc,
scom_op->addr, scom_op->read, scom_op->data);
}
}
src/occ_gpe0/apss_util.h
View file @ 76a5df9b
......@@ -27,6 +27,9 @@
#define _APSS_UTIL_H
#include <apss_structs.h>
#include <common_types.h>
#include <ipc_structs.h>
#include <ipc_async_cmd.h>
void apss_set_ffdc(GpeErrorStruct *o_error, uint32_t i_addr, uint32_t i_rc, uint64_t i_ffdc);
......
src/occ_gpe0/img_defs.mk
View file @ 76a5df9b
......@@ -94,6 +94,10 @@ ifndef COMMONLIB_SRCDIR
export COMMONLIB_SRCDIR = $(abspath ../lib/common)
endif
ifndef OCC_COMMON_TYPES_DIR
export OCC_COMMON_TYPES_DIR = $(abspath ../occ_405/incl/)
endif
ifndef OCCLIB_SRCDIR
export OCCLIB_SRCDIR = $(abspath ../lib/occlib)
endif
......@@ -177,7 +181,8 @@ DEFS += $(GCC-DEFS)
INCLUDES += $(IMG_INCLUDES) $(GLOBAL_INCLUDES) \
-I$(PK_SRCDIR)/kernel -I$(PK_SRCDIR)/ppe42 -I$(PK_SRCDIR)/trace \
-I$(PK_SRCDIR)/$(PPE_TYPE) -I$(PK_SRCDIR)/../../include \
-I$(PK_SRCDIR)/../../include/registers -I$(OCCLIB_SRCDIR) -I$(COMMONLIB_SRCDIR)
-I$(PK_SRCDIR)/../../include/registers -I$(OCCLIB_SRCDIR) -I$(COMMONLIB_SRCDIR) \
-I$(OCC_COMMON_TYPES_DIR)
PIPE-CFLAGS = -pipe -Wa,-m405
......
src/occ_gpe0/ipc_func_tables.c
View file @ 76a5df9b
......@@ -24,12 +24,14 @@
/* IBM_PROLOG_END_TAG */
#include "ipc_api.h"
#include "ipc_ping.h"
#include "apss_util.h"
void apss_init_gpio(ipc_msg_t* cmd, void* arg);
void apss_init_mode(ipc_msg_t* cmd, void* arg);
void apss_start_pwr_meas_read(ipc_msg_t* cmd, void* arg);
void apss_continue_pwr_meas_read(ipc_msg_t* cmd, void* arg);
void apss_complete_pwr_meas_read(ipc_msg_t* cmd, void* arg);
void ipc_scom_operation(ipc_msg_t* cmd, void* arg);
extern ipc_msgq_t G_gpe0_test_msgq0;
......@@ -59,7 +61,7 @@ IPC_HANDLER(apss_init_mode, 0) // 2 - IPC_ST_APSS_INIT_MODE_FUNCID
IPC_HANDLER(apss_start_pwr_meas_read, 0) // 3 - IPC_ST_APSS_START_PWR_MEAS_READ_FUNCID
IPC_HANDLER(apss_continue_pwr_meas_read, 0) // 4 - IPC_ST_APSS_CONTINUE_PWR_MEAS_READ_FUNCID
IPC_HANDLER(apss_complete_pwr_meas_read, 0) // 5 - IPC_ST_APSS_COMPLETE_PWR_MEAS_READ_FUNCID
IPC_HANDLER_DEFAULT // 6
IPC_HANDLER(ipc_scom_operation, 0) // 6 - IPC_ST_SCOM_OPERATION
IPC_HANDLER_DEFAULT // 7
IPC_HANDLER_DEFAULT // 8
IPC_HANDLER_DEFAULT // 9
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment

Powered by Integricloud