GitLab

Corresponding to flashrom svn r1846.
Signed-off-by: Michael Coppola <michael.n.coppola@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

The Wildcat Point PCH can be paired with Broadwell or Haswell.
This patch was essentially backported from ChromiumOS commit 9bd2af8.

Corresponding to flashrom svn r1845.
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

The core of this patch to support Bay Trail originally came from the
Chromiumos flashrom repo and was modified by Sage to support the
Rangeley/Avoton parts as well.
Because that was not complicated enough already Stefan Tauner refactored
and refined everything. Bay Trail seems to be the first Atom SoC able to
support hwseq. No SPI Programming Guide could be obtained so it is
handled similarly to Lynx Point which seems to be its nearest relative.

Corresponding to flashrom svn r1844.
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested-by: Marc Jones <marcj303@gmail.com>
Tested-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested-by: Thomas Reardon <thomas_reardon@hotmail.com>
Tested-by: Wen Wang <wen.wang@adiengineering.com>
Acked-by: Marc Jones <marcj303@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

Possible values as well as encodings have changed in newer chipsets as follows.
 - Pre-PCH (i.e. ICH) chipsets had a maximum frequency of 33 MHz for all
   operations
 - Since Cougar Point the chipsets support dual output fast reads (encoded
   in bit 30).
 - Flash component density encoding has changed from 3 to 4 bits with Lynx
   Point, currently allowing for up to 64 MB chips.

Corresponding to flashrom svn r1843.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

 - Change check_max_decode() to return the number of (common) busses
   where the flash chip exceeds the supported size of the programmer.
 - Refine its signature to use a flashctx pointer only.
 - Move CLI-related bits to cli_classic.c.
 - Rename check_max_decode() to count_max_decode_exceedings() to
   better reflect what it (now) really does.
 - Refine the messages printed by the caller to better integrate with the new
   setup, and simplify them.

Corresponding to flashrom svn r1842.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Begin to move functions that clearly belong to the (command line)
user interface out of flashrom's core files like flashrom.c.

 - Refine messages within check_chip_supported(), rename it to
   print_chip_support_status() and move it to newly created cli_common.c.
 - Move flashbuses_to_text() to cli_common.c as well.
 - Move global verbosity variables to cli_output.c.

Corresponding to flashrom svn r1841.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Some Parallel bus chips have a 16-bit mode and an 8-bit mode. They use
normal JEDEC addresses for 16-bit mode and shifted addresses (by 1 bit)
for 8-bit mode. Some programmers can access them in 16-bit mode, but on
all flashrom-supported programmers so far, we access them in 8-bit mode.
This means we have to shift the addresses but apart from the addresses
we can share the code.

This patch makes this possible by checking the chip's FEATURE_ADDR_SHIFTED
flag in common JEDEC functions and applying the right addresses respectively.

Corresponding to flashrom svn r1840.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Tested mainboards:
OK:
 - ASUS F2A85-M
   Reported by various corebooters
 - ASUS M2N-MX SE Plus
   Reported by Antonio
 - ASUS P5LD2
   Reported by François Revol
 - Lenovo ThinkPad T530
   Reported and partially authored by Edward O'Callaghan
 - MSI MS-7502 (Medion MD8833)
   Reported by naq on IRC
 - Shuttle AB61
   Reported by olofolleola4
 - ZOTAC IONITX-F-E
   Reported by Bernardo Kuri

Flash chips:
 - Atmel AT45DB021D to PREW (+PREW)
   Reported by The Raven
 - Atmel AT25F4096 to PREW (+PREW)
   Reported by 공준혁
 - GigaDevice GD25Q16(B) to PREW (+PREW)
   Reported by luxflow@live.com using a GD25Q16BSIG
 - Catalyst CAT28F512
   Mark erase and write as known bad (not implemented)

Miscellaneous:
 - Various spelling corrections by Daniele Forsi.
 - Added and refined a bunch of chips originally investigated by Carl-Daniel.
 - Marked the ARM-USB-OCD-H programmer as tested
   (reported by Ruud Schramp).
 - Tiny other stuff.

Corresponding to flashrom svn r1839.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

Additionally to the existing S25FL128S......0 definition this patch
adds S25FL128P......0, S25FL128P......1 and S25FL128S......1, as well as
S25FL129P......0 and S25FL129P......1 definitions.
S25FL12xP seem to be the predecessor families of S25FL128S. All
associated chips can not be distinguished with RDID alone.

Besides the new chips, this patch also fixes the name of the  previously
supported S25FL128S model with uniform 256 kB sectors
(S25FL128P......1 not 0) and adds the hybrid sector version (0) as well.

Due to the shared IDs the user has to select the right chip manually
with the -c parameter. To make this even possible, this patch enlarges
the respective array for results to 6.
Tested-by: Antonio Ospite <ao2@ao2.it>
with a S25FL129P......0.

Corresponding to flashrom svn r1838.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

Apparently the erase function did never set any address before issuing the
erase commands. How could this ever work?
Also, according to PCH documentation crossing 256 byte boundaries is invalid
and may cause wraparound due to the flash chip's pages. Check for this on
reads as well as writes.

Thanks to Vladimir 'φ-coder/phcoder' Serbinenko for noticing these issues
and providing the initial patch.

Corresponding to flashrom svn r1837.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

For arm64 with 32-bit userspace, pointers such as 0xff96ebf8 were
incorrectly getting converted to u64_t 0xffffffffff96ebf8 in the
spi_ioc_transfer struct which was causing ioctl()s to be rejected by
the kernel. With this patch we first cast to uintptr_t (to avoid
warnings on architectures where char * are not 64b wide) and then to
uint64_t which is always big enough and does not produce warnings.

This patch is taken from ChromiumOS'
Change-Id: I5a15b4ca5d9657c3cb1ddccd42eafd91c852dd26

Corresponding to flashrom svn r1836.
Signed-off-by: David Riley <davidriley@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

29GL chips use a new 3-Byte device ID probing function at addresses
0x01, 0x0E, 0x0F.

Flash chip families supported by this method include...
 - EON EN29GL
 - Gigadevice GD29GL (if they really exist)
 - ISSI (PMC) IS29GL
 - Macronix MX29GL (+MX68GL1G0F)
 - Spansion S29GL (+S70GL02G)
 - Winbond W29GL

This patch adds respective flash chip definitions for chips up to 16 MB from
Eon, ISSI, Macronix and Winbond. Bigger chips as well as those from
Gigadevice and Spansion are left out.

Corresponding to flashrom svn r1835.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

Also, slightly refine the definition of AT49LH002.

Corresponding to flashrom svn r1834.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

This includes PMC Pm49*, SST 49LF00*, ST M50* and Winbond W39* families.
The erase and write test status bits of all affected chips have been reset.

Corresponding to flashrom svn r1833.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

This patch lets you read and write the EEPROM on 82580-based gigabit NIC
cards. So far it has been tested on copper NICs only, but other variants
employing this controller should work too.
It is a nice substitution for the official eeupdate tool.

Speed is quite decent: less than 4 seconds for erases or writes of 32 kB.

Corresponding to flashrom svn r1832.
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

Register_programmer suggests that we register a programmer. However,
that function registers a master for a given bus type, and a programmer
may support multiple masters (e.g. SPI, FWH). Rename a few other
functions to be more consistent.

Corresponding to flashrom svn r1831.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

SPI controller on the bolton chipset uses the same 3-bit speed
settings as Yangtze, but is otherwise the same as the Hudson chips.
Note that the Bolton RRG doesn't specify a speed setting for the bit
setting of 0b111, so I'm assuming that it's the same setting as
Yangtze.

Corresponding to flashrom svn r1830.
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

Corresponding to flashrom svn r1829.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

ASUS Vintage 2 PH1 barebone systems have a mainboard from the P5LD2 series,
namely the P5LD2-MQ (although it is labeled V2-PH1). Pin 16 GPIO needs to
be raised to enable write/erase like on other boards of the series.
NB: it uses a ICH7DH southbridge and hence requires different PCI IDs.

Corresponding to flashrom svn r1828.
Signed-off-by: Dima Veselov <kab00m@lich.phys.spbu.ru>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

Without this...
Erasing and writing flash chip... ERASE FAILED at 0x00001000! Expected=0xff, Read=0xb4, failed byte count from 0x00000000-0x0000ffff: 0xef09
ERASE FAILED!
Reading current flash chip contents... done.
<loooooong break while the next eraser and writing is tried>
Erase/write done.
Verifying flash... VERIFIED.

Even if there is not a long temporal pause, it is very confusing for
the user to first see a failed erase, followed by a read, a done
message and eventually the verification message.
This patch inserts "Looking for another erase function." where there is
just a silent pause above.

Corresponding to flashrom svn r1827.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

This should get rid of extra and/or missing line breaks in verbose(+)
output on Intel chipsets.

Corresponding to flashrom svn r1826.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

The MX29F022(N)T definition was successfully tested by Daniele.

Corresponding to flashrom svn r1825.
Signed-off-by: Daniele Forsi <dforsi@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

Previously we tried to replace garbage characters with <space> directly in
the read-only memory-mapped SMBIOS area(!). This could never have
worked for any DMI strings with garbage and results in a segfault on
machines with such strings.

Thanks to Brian Rak (Supermicro X10SLE-F) and John Pohlman (HP XW9400)
for reporting this issue.

With this patch the strings are duplicated within dmi_string() already,
just before we sanitize them. Also, the limit variable used everywhere
points to the first invalid byte address. Refine respective checks
accordingly.

Corresponding to flashrom svn r1824.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Corresponding to flashrom svn r1823.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

Add support for EEPROMs with 1 byte granularity and implicit erase on
write. flashrom will not try to erase before write on these chips.
Explicitly requested erase with -E is done by writing 0xff.

Corresponding to flashrom svn r1822.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

Check for NULL termination of the array, that each board has the two
main PCI ID sets defined, that coreboot vendor and model fields are either
both set or unset, and that at least either an enable function or a max
decode size is available.

Corresponding to flashrom svn r1821.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

We got enough (and no one is looking at them for the time being anyway).
Also, return an error code in the case no bus type could be detected.

Corresponding to flashrom svn r1820.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Move some suitable functions there, add it to the Makefile, but leave the
declarations in flash.h for now.

Corresponding to flashrom svn r1819.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Also, add spi_disable_blockprotect_bp1_srwd().

Originally written and tested by The Raven <originalraven@hotmail.com>.

Corresponding to flashrom svn r1818.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

ISO 8601.

Corresponding to flashrom svn r1817.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

Corresponding to flashrom svn r1816.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

Mark all ME-enabled Intel chipsets as DEP, alter print.c accordingly
(print_wiki.c was already prepared). And realign the chipset enable
table when we are at it already.

Corresponding to flashrom svn r1815.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

This code exists thanks to food for thought from Urja Rannikko.

Corresponding to flashrom svn r1814.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Corresponding to flashrom svn r1813.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

This PCI PATA controller can use 3V parallel flash up to 128 kB.

My card was identified as:
  PCI 1283:8212, subsystem 1283:0001.

and labelled as:
  Innovision Multimedia LTD.
  EIO ATA133 RAID
  (DM-8401 Ver A)

This particular card did not require setting of any GPIO signals to
enable flash writing. My card has Pm39LV512 in PLCC32 package without
socket.

Rebased by Stefan (automatic cleanup, some PCI changes, changed
enable bit handling). Committed with test state NT because the
rebased version was not tested on real hardware (yet).

Corresponding to flashrom svn r1812.
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Corresponding to flashrom svn r1811.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

Corresponding to flashrom svn r1810.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

Due to the mysterious address handling of this chip the user can specify
a base address with the offset parameter, e.g.:
flashrom -p atavia:offset=0xFFF00000

Thanks to Idwer Vollering for his iterative testing of this code, as well as to
Martijn Bastiaan who did the last tests before merging.

Corresponding to flashrom svn r1809.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

This patch combines two identical block and chip erase functions respectively:
 - Merge block_erase_m29f400bt and block_erase_en29lv640b into
   erase_block_shifted_jedec.
 - Merge block_erase_chip_m29f400bt and block_erase_chip_en29lv640b into
   erase_chip_block_shifted_jedec.

Leave their implementations in en29lv640b.c for now.

Corresponding to flashrom svn r1808.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Add headers and columns (i.e. print device entries in a table-like manner).
Also, add and use test_state_to_text() to support the new test states.

Corresponding to flashrom svn r1807.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>