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  1. 15 Sep, 2010 5 commits
    • Carl-Daniel Hailfinger's avatar
      Detect embedded EC (IMC) in AMD's SBs · 39446e34
      Carl-Daniel Hailfinger authored 
      
AMD SB700 and later have an integrated microcontroller (IMC) which runs
from shared flash.

The IMC will happily issue reads while we write, issue writes while we
read, and generally cause lots of havoc due to the concurrent accesses
it performs while flashrom is running. A failing or corrupted read can
be detected since r1145, and the worst case is that the read aborts and
the user has to retry. A failing write is much more serious. It can
be detected since r1145, but if the SPI interface locks up, we can't
continue writing nor can we read the current chip contents.

If the IMC is inactive, there is no reason to worry. If the IMC is
active, flashrom will refuse to erase/write the chip with this patch.

The correct fix would be to stop the IMC during flashing, but apparently
the relevant registers are undocumented, so we take the safe route for
now until someone from AMD can give us more info.

Corresponding to flashrom svn r1173.
Signed-off-by: default avatarCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested-by: default avatarMatthias Kretz <kretz@kde.org>
Acked-by: default avatarUwe Hermann <uwe@hermann-uwe.de>
      39446e34
    • Carl-Daniel Hailfinger's avatar
      Delay between probe and subsequent operations · 9ad4255b
      Carl-Daniel Hailfinger authored 
      
Some flash chips need time to exit ID mode, and while we take care of
correct timing for the matching probe, subsequent probes may have
totally different timing, and that can lead to garbage responses from
the flash chip during the first accesses after the probe sequence is
done.
Delay 100 ms between the last probe and any subsequent operation.
To ensure maximum correctness, we would have to reset the chip first in
case the last probe function left the chip in an undefined (non-read)
state. That will be possible once struct flashchip has a .reset
function.

This fixes unstable erase/read/write for some flahs chips on nic3com and
possible other use cases as well.

Thanks to Maciej Pijanka for reporting the issue and testing patches.

Corresponding to flashrom svn r1172.
Signed-off-by: default avatarCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: default avatarMichael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
      9ad4255b
    • Carl-Daniel Hailfinger's avatar
      SPI bitbanging: request/release bus · 2822888c
      Carl-Daniel Hailfinger authored 
      
SPI bitbanging on devices which speak SPI natively has a dual-use
problem: We need to shut down normal SPI operations to do the bitbanging
ourselves. Once we're done, it makes a lot of sense to reenable "normal"
SPI operations again. Add request_bus/release_bus functions to struct
bitbang_spi_master.
Add a bitbang shutdown function (not used yet).
Change MCP SPI and Intel NIC SPI to use the new request/release bus
infrastructure.
Cosmetic changes to a few error messages (80 column limit).

There are multiple possible strategies for bus request/release:
- Request at the start of a SPI command, release immediately afterwards.
- Request at the start of a SPI multicommand, release once all commands
of the multicommand are done.
- Request on programmer init, release on shutdown.
Each strategy has its own advantages. For now, we will stay with the
first strategy which worked fine so far.

Corresponding to flashrom svn r1171.
Signed-off-by: default avatarCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: default avatarUwe Hermann <uwe@hermann-uwe.de>
      2822888c
    • Carl-Daniel Hailfinger's avatar
      Honor ICH SPI address window for reads · ec489e4e
      Carl-Daniel Hailfinger authored 
      
ICH SPI has the ability to restrict SPI read/write accesses to a given
address range. The low end of the range is configurable by the BIOS (and
by flashrom if the BIOS didn't lock down the flash interface), the high
end of the range is 0xffffff (2^24-1).
This patch checks for an address range restriction and uses the low end
of the allowed range as base for SPI reads. A similar workaround for
REMS/RES opcodes has been committed in r500.

This fixes read on the Intel D945GCLF mainboard where the stock BIOS
enforces a restricted address range.
Please note that writes need the same fix, but for architectural reasons
that fix will be merged once partial write is available.

Corresponding to flashrom svn r1170.
Signed-off-by: default avatarCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Tested by David Hendricks on the Intel D945GCLF mainboard, results at
http://paste.flashrom.org/view.php?id=79

Acked-by: default avatarDavid Hendricks <dhendrix@google.com>
      ec489e4e
    • Uwe Hermann's avatar
      Add missing GIGABYTE GA-7DXR entry, should have been in r1166 · 9a87c5d6
      Uwe Hermann authored 
      
Corresponding to flashrom svn r1169.
Signed-off-by: default avatarUwe Hermann <uwe@hermann-uwe.de>
Acked-by: default avatarUwe Hermann <uwe@hermann-uwe.de>
      9a87c5d6
  3. 14 Sep, 2010 5 commits
  5. 13 Sep, 2010 5 commits
  7. 11 Sep, 2010 1 commit
  9. 10 Sep, 2010 2 commits
  11. 07 Sep, 2010 2 commits
  13. 05 Sep, 2010 1 commit
  15. 04 Sep, 2010 1 commit
  17. 03 Sep, 2010 5 commits
  19. 01 Sep, 2010 1 commit
  21. 18 Aug, 2010 1 commit
    • Carl-Daniel Hailfinger's avatar
      Add paranoid checks to sb600spi driver · eb0e7fc4
      Carl-Daniel Hailfinger authored 
      
Add paranoid checks for correct values in essential registers in the SB600/SB700/... SPI driver. If something else changes the values we
wrote, we will see severe read/write corruption.
sb600spi will now abort the access and return an error if it detects
this sort of corruption.

Note: This corruption can be caused by a few different events:
- IPMI/BMC/IMC accesses flash
- Other software accesses flash
The nature of flash access (read/write/ID/...) is irrelevant. Each such
access will cause corruption for all other accesses happening at the
same time.

Thanks to Matthias Kretz for testing this patch.

Corresponding to flashrom svn r1145.
Signed-off-by: default avatarCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: default avatarMatthias Kretz <kretz@kde.org>
      eb0e7fc4
  23. 16 Aug, 2010 1 commit
  25. 15 Aug, 2010 5 commits
  27. 13 Aug, 2010 1 commit
  29. 11 Aug, 2010 1 commit
  31. 08 Aug, 2010 3 commits

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