Add a bunch of new/tested stuff and various small changes 14

Tested Mainboards:
OK:
 - ASUS M3A78-EH
   http://www.flashrom.org/pipermail/flashrom/2010-October/005297.html
 - ASUS P2B-LS
   http://www.flashrom.org/pipermail/flashrom/2010-November/005506.html
 - Biostar TA790GX A3+
   http://paste.flashrom.org/view.php?id=1350
 - ECS 848P-A7
   http://www.flashrom.org/pipermail/flashrom/2011-January/005781.html
 - GIGABYTE GA-G41MT-S2PT
   Reported on IRC
 - GIGABYTE GA-H77-D3H
   Reported and tested by Alexander Gordeev on IRC.
 - Gigabyte GA-X79-UD5
   http://www.flashrom.org/pipermail/flashrom/2012-August/009811.html
 - Shuttle FN78S
   http://www.flashrom.org/pipermail/flashrom/2012-August/009714.html
 - VIA EITX-3000
   Reported on IRC by Tuju

NOT OK:
 - Dell PowerEdge C6220 (0HYFFG)
   http://www.flashrom.org/pipermail/flashrom/2012-September/009900.html
 - Foxconn Q45M
   http://www.flashrom.org/pipermail/flashrom/2012-September/009923.html
 - MSI MS-7309 (K9N6SGM-V)
   http://www.flashrom.org/pipermail/flashrom/2012-August/009712.html
 - Supermicro X9QRi-F+
   http://www.flashrom.org/pipermail/flashrom/2012-September/009887.html
 - ZOTAC H61-ITX WiFi (H61ITX-A-E)
   http://www.flashrom.org/pipermail/flashrom/2012-August/009649.html

ASUS CUSL2-C has been tested to be working with the board enable once
implemented for the TUSL2-C board. They seem to have the same PCI IDs
as shown in the links below. Since only the CUSL2-C board enable has been
tested yet, we distinguish the two by DMI strings.
http://paste.flashrom.org/view.php?id=1393
http://www.flashrom.org/pipermail/flashrom/attachments/20091206/ddca2c6c/attachment-0002.eml

Tested flash chips:
 - Set EMST F25L008A to PREW (+PREW)
   http://www.flashrom.org/pipermail/flashrom/2012-August/009714.html
 - Set GigaDevice GD25Q64 to PREW (+PREW)
   http://git.chromium.org/gitweb/?p=chromiumos/third_party/flashrom.git;a=commit;h=9e8ef49b1f626c2197e131fba6c5b65c8af4eeea
 - Set Macronix MX25L12805 to P (+P)
   http://www.flashrom.org/pipermail/flashrom/2012-September/009887.html
 - Set SST SST49LF003A/B to PREW (+EW)
   http://paste.flashrom.org/view.php?id=467
 - Set Winbond W49V002FA to PREW (+EW)
   http://www.flashrom.org/pipermail/flashrom/2011-January/005781.html

Tested chipsets:
 - Intel X79 (0x1d41)
   http://www.flashrom.org/pipermail/flashrom/2012-August/009811.html

Board enables:
 - add ASUS P4P800-X
   Created by Idwer Vollering and tested by Mingsen Bao:
   http://paste.flashrom.org/view.php?id=467


 - add DMI string to P4P800-VM

Miscellaneous:
 - Add remaining Intel 7 series chipset (LPC) PCI IDs
 - Add generic SPI detection for chips from Winbond
 - Minor manpage changes
 - Minor other cleanups
 - Escape full stops after abbreviations in the manpage.
 - Add ICH9 and successors to spi_get_valid_read_addr

Corresponding to flashrom svn r1601.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

board_enable.c

@@ -346,7 +346,7 @@ void probe_superio_winbond(void)
 		case WINBOND_W83627HF_ID:
 		case WINBOND_W83627EHF_ID:
 		case WINBOND_W83627THF_ID:
-			msg_pdbg("Found Winbond Super I/O, id %02hx\n", s.model);
+			msg_pdbg("Found Winbond Super I/O, id 0x%02hx\n", s.model);
 			register_superio(s);
 			break;
 		case WINBOND_W83697HF_ID:
@@ -355,7 +355,7 @@ void probe_superio_winbond(void)
 			if (((tmp == 0x00) && (s.port != WINBOND_SUPERIO_PORT1)) ||
 			    ((tmp == 0x40) && (s.port != WINBOND_SUPERIO_PORT2))) {
 				msg_pdbg("Winbond Super I/O probe weirdness: Port mismatch for ID "
-					 "%02x at port %04x\n", s.model, s.port);
+					 "0x%02x at port 0x%04x\n", s.model, s.port);
 				break;
 			}
 			tmp = w836xx_deviceid_hwmon(s.port);
@@ -365,11 +365,11 @@ void probe_superio_winbond(void)
 				break;
 			}
 			if (tmp != s.model) {
-				msg_pinfo("W83 series hardware monitor device ID weirdness: expected %02x, "
-					  "got %02x\n", WINBOND_W83697HF_ID, tmp);
+				msg_pinfo("W83 series hardware monitor device ID weirdness: expected 0x%02x, "
+					  "got 0x%02x\n", WINBOND_W83697HF_ID, tmp);
 				break;
 			}
-			msg_pinfo("Found Winbond Super I/O, id %02hx\n", s.model);
+			msg_pinfo("Found Winbond Super I/O, id 0x%02hx\n", s.model);
 			register_superio(s);
 			break;
 		}
@@ -1700,11 +1700,13 @@ static int intel_ich_gpio20_raise(void)
 
 /*
  * Suited for:
+ *  - ASUS CUSL2-C: Intel socket370 + 815 + ICH2
  *  - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2
  *  - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5
  *  - ASUS P4P800: Intel socket478 + 865PE + ICH5R
  *  - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R
  *  - ASUS P4P800-VM: Intel socket478 + 865PE + ICH5R
+ *  - ASUS P4P800-X: Intel socket478 + 865PE + ICH5R
  *  - ASUS P5GD1 Pro: Intel LGA 775 + 915P + ICH6R
  *  - ASUS P5GD2 Premium: Intel LGA775 + 915G + ICH6R
  *  - ASUS P5GDC Deluxe: Intel socket775 + 915P + ICH6R
@@ -2333,8 +2335,9 @@ const struct board_match board_matches[] = {
 	{0x8086, 0x2560, 0x103C, 0x2A00,  0x8086, 0x24C3, 0x103C, 0x2A01, "^Guppy",     NULL, NULL,           P3, "ASUS",        "P4GV-LA (Guppy)",       0,   OK, intel_ich_gpio21_raise},
 	{0x8086, 0x24D3, 0x1043, 0x80A6,  0x8086, 0x2578, 0x1043, 0x80F6, NULL,         NULL, NULL,           P3, "ASUS",        "P4C800-E Deluxe",       0,   OK, intel_ich_gpio21_raise},
 	{0x8086, 0x2570, 0x1043, 0x80F2,  0x8086, 0x24D5, 0x1043, 0x80F3, NULL,         NULL, NULL,           P3, "ASUS",        "P4P800",                0,   NT, intel_ich_gpio21_raise},
-	{0x8086, 0x2570, 0x1043, 0x80F2,  0x8086, 0x24D3, 0x1043, 0x80A6, "^P4P800-E$", NULL, NULL,           P3, "ASUS",        "P4P800-E Deluxe",       0,   OK, intel_ich_gpio21_raise},
-	{0x8086, 0x2570, 0x1043, 0x80A5,  0x8086, 0x24d0,      0,      0, NULL,         NULL, NULL,           P3, "ASUS",        "P4P800-VM",             0,   OK, intel_ich_gpio21_raise},
+	{0x8086, 0x2570, 0x1043, 0x80f2,  0x8086, 0x24d3, 0x1043, 0x80a6, "^P4P800-E$", NULL, NULL,           P3, "ASUS",        "P4P800-E Deluxe",       0,   OK, intel_ich_gpio21_raise},
+	{0x8086, 0x2570, 0x1043, 0x80a5,  0x8086, 0x24d3, 0x1043, 0x80a6, "^P4P800-VM$", NULL, NULL,          P3, "ASUS",        "P4P800-VM",             0,   OK, intel_ich_gpio21_raise},
+	{0x8086, 0x2570, 0x1043, 0x80f2,  0x8086, 0x24d3, 0x1043, 0x80a6, "^P4P800-X$", NULL, NULL,           P3, "ASUS",        "P4P800-X",              0,   OK, intel_ich_gpio21_raise},
 	{0x1039, 0x0651, 0x1043, 0x8081,  0x1039, 0x0962,      0,      0, NULL,         NULL, NULL,           P3, "ASUS",        "P4SC-E",                0,   OK, it8707f_write_enable_2e},
 	{0x8086, 0x2570, 0x1043, 0x80A5,  0x105A, 0x24D3, 0x1043, 0x80A6, NULL,         NULL, NULL,           P3, "ASUS",        "P4SD-LA",               0,   NT, intel_ich_gpio32_raise},
 	{0x1039, 0x0661, 0x1043, 0x8113,  0x1039, 0x5513, 0x1043, 0x8087, NULL,         NULL, NULL,           P3, "ASUS",        "P4S800-MX",             512, OK, w836xx_memw_enable_2e},
@@ -2356,8 +2359,9 @@ const struct board_match board_matches[] = {
 	{0x10DE, 0x0260, 0x1043, 0x81BC,  0x10DE, 0x026C, 0x1043, 0x829E, "^P5N-D$",    NULL, NULL,           P3, "ASUS",        "P5N-D",                 0,   OK, it8718f_gpio63_raise},
 	{0x10DE, 0x0260, 0x1043, 0x81BC,  0x10DE, 0x026C, 0x1043, 0x8249, "^P5N-E SLI$",NULL, NULL,           P3, "ASUS",        "P5N-E SLI",             0,   NT, it8718f_gpio63_raise},
 	{0x8086, 0x24dd, 0x1043, 0x80a6,  0x8086, 0x2570, 0x1043, 0x8157, NULL,         NULL, NULL,           P3, "ASUS",        "P5PE-VM",               0,   OK, intel_ich_gpio21_raise},
-	{0x8086, 0x2443, 0x1043, 0x8027,  0x8086, 0x1130, 0x1043, 0x8027, NULL,         NULL, NULL,           P3, "ASUS",        "TUSL2-C",               0,   NT, intel_ich_gpio21_raise},
-	{0x1106, 0x3177, 0x1106, 0x3177,  0x1106, 0x3116, 0x1106, 0x3116, "^KM266-8235$", "biostar", "m7viq",         P3, "Biostar",     "M7VIQ",                 0,   NT, w83697xx_memw_enable_2e},
+	{0x8086, 0x2443, 0x1043, 0x8027,  0x8086, 0x1130, 0x1043, 0x8027, "^CUSL2-C",   NULL, NULL,           P3, "ASUS",        "CUSL2-C",               0,   OK, intel_ich_gpio21_raise},
+	{0x8086, 0x2443, 0x1043, 0x8027,  0x8086, 0x1130, 0x1043, 0x8027, "^TUSL2-C",   NULL, NULL,           P3, "ASUS",        "TUSL2-C",               0,   NT, intel_ich_gpio21_raise},
+	{0x1106, 0x3177, 0x1106, 0x3177,  0x1106, 0x3116, 0x1106, 0x3116, "^KM266-8235$", "biostar", "m7viq", P3, "Biostar",     "M7VIQ",                 0,   NT, w83697xx_memw_enable_2e},
 	{0x10b7, 0x9055, 0x1028, 0x0082,  0x8086, 0x7190,      0,      0, NULL,         NULL, NULL,           P3, "Dell",        "OptiPlex GX1",          0,   OK, intel_piix4_gpo30_lower},
 	{0x8086, 0x3590, 0x1028, 0x016c,  0x1000, 0x0030, 0x1028, 0x016c, NULL,         NULL, NULL,           P3, "Dell",        "PowerEdge 1850",        0,   OK, intel_ich_gpio23_raise},
 	{0x1106, 0x3189, 0x1106, 0x3189,  0x1106, 0x3177, 0x1106, 0x3177, "^AD77",      "dfi", "ad77",        P3, "DFI",         "AD77",                  0,   NT, w836xx_memw_enable_2e},

chipdrivers.h

@@ -27,7 +27,12 @@
 
 #include "flash.h"	/* for chipaddr and flashctx */
 
-/* spi.c, should probably be in spi_chip.c */
+/* spi.c */
+int spi_aai_write(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
+int spi_chip_write_256(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
+int spi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start, int unsigned len);
+
+/* spi25.c */
 int probe_spi_rdid(struct flashctx *flash);
 int probe_spi_rdid4(struct flashctx *flash);
 int probe_spi_rems(struct flashctx *flash);
@@ -44,8 +49,6 @@ int spi_block_erase_62(struct flashctx *flash, unsigned int addr, unsigned int b
 int spi_block_erase_c7(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
 erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode);
 int spi_chip_write_1(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
-int spi_chip_write_256(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
-int spi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start, int unsigned len);
 uint8_t spi_read_status_register(struct flashctx *flash);
 int spi_write_status_register(struct flashctx *flash, int status);
 void spi_prettyprint_status_register_bit(uint8_t status, int bit);
@@ -58,7 +61,6 @@ int spi_nbyte_program(struct flashctx *flash, unsigned int addr, uint8_t *bytes,
 int spi_nbyte_read(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len);
 int spi_read_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize);
 int spi_write_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize);
-int spi_aai_write(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
 
 /* sfdp.c */
 int probe_spi_sfdp(struct flashctx *flash);

chipset_enable.c

@@ -1405,17 +1405,22 @@ const struct penable chipset_enables[] = {
 	{0x8086, 0x1c56, NT, "Intel", "C206",		enable_flash_pch6},
 	{0x8086, 0x1c5c, OK, "Intel", "H61",		enable_flash_pch6},
 	{0x8086, 0x1d40, OK, "Intel", "X79",		enable_flash_pch6},
-	{0x8086, 0x1d41, NT, "Intel", "X79",		enable_flash_pch6},
+	{0x8086, 0x1d41, OK, "Intel", "X79",		enable_flash_pch6},
 	{0x8086, 0x1e44, NT, "Intel", "Z77",		enable_flash_pch7},
 	{0x8086, 0x1e46, NT, "Intel", "Z75",		enable_flash_pch7},
+	{0x8086, 0x1e47, NT, "Intel", "Q77",		enable_flash_pch7},
+	{0x8086, 0x1e48, NT, "Intel", "Q75",		enable_flash_pch7},
 	{0x8086, 0x1e49, NT, "Intel", "B75",		enable_flash_pch7},
 	{0x8086, 0x1e4a, NT, "Intel", "H77",		enable_flash_pch7},
+	{0x8086, 0x1e53, NT, "Intel", "C216",		enable_flash_pch7},
 	{0x8086, 0x1e55, OK, "Intel", "QM77",		enable_flash_pch7},
+	{0x8086, 0x1e56, NT, "Intel", "QS77",		enable_flash_pch7},
 	{0x8086, 0x1e57, NT, "Intel", "HM77",		enable_flash_pch7},
 	{0x8086, 0x1e58, NT, "Intel", "UM77",		enable_flash_pch7},
 	{0x8086, 0x1e59, NT, "Intel", "HM76",		enable_flash_pch7},
 	{0x8086, 0x1e5d, NT, "Intel", "HM75",		enable_flash_pch7},
 	{0x8086, 0x1e5e, NT, "Intel", "HM70",		enable_flash_pch7},
+	{0x8086, 0x1e5f, NT, "Intel", "NM70",		enable_flash_pch7},
 	{0x8086, 0x2310, NT, "Intel", "DH89xxCC",	enable_flash_pch7},
 	{0x8086, 0x2410, OK, "Intel", "ICH",		enable_flash_ich_4e},
 	{0x8086, 0x2420, OK, "Intel", "ICH0",		enable_flash_ich_4e},

flash.h

@@ -58,6 +58,21 @@ enum chipbustype {
 	BUS_NONSPI	= BUS_PARALLEL | BUS_LPC | BUS_FWH,
 };
 
+/*
+ * The following write granularities are known:
+ * - 1 bit: Each bit can be cleared individually.
+ * - 1 byte: A byte can be written once. Further writes to an already written byte cause its contents to be
+ *   either undefined or to stay unchanged.
+ * - 128 bytes: If less than 128 bytes are written, the rest will be erased. Each write to a 128-byte region
+ *   will trigger an automatic erase before anything is written. Very uncommon behaviour.
+ * - 256 bytes: If less than 256 bytes are written, the contents of the unwritten bytes are undefined.
+ */
+enum write_granularity {
+	write_gran_1bit,
+	write_gran_1byte,
+	write_gran_256bytes,
+};
+
 /*
  * How many different contiguous runs of erase blocks with one size each do
  * we have for a given erase function?
@@ -203,11 +218,6 @@ void print_supported(void);
 void print_supported_wiki(void);
 
 /* flashrom.c */
-enum write_granularity {
-	write_gran_1bit,
-	write_gran_1byte,
-	write_gran_256bytes,
-};
 extern int verbose_screen;
 extern int verbose_logfile;
 extern const char flashrom_version[];

flashchips.c

@@ -2596,7 +2596,7 @@ const struct flashchip flashchips[] = {
 		.total_size	= 1024,
 		.page_size	= 256,
 		.feature_bits	= FEATURE_WRSR_EITHER,
-		.tested		= TEST_UNTESTED,
+		.tested		= TEST_OK_PREW,
 		.probe		= probe_spi_rdid,
 		.probe_timing	= TIMING_ZERO,
 		.block_erasers	=
@@ -3474,7 +3474,7 @@ const struct flashchip flashchips[] = {
 		.unlock		= spi_disable_blockprotect,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read,
-		.voltage        = {2700, 3600},
+		.voltage	= {2700, 3600},
 	},
 
 	{
@@ -3509,7 +3509,7 @@ const struct flashchip flashchips[] = {
 		.unlock		= spi_disable_blockprotect,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read,
-		.voltage        = {2700, 3600},
+		.voltage	= {2700, 3600},
 	},
 
 	{
@@ -3585,7 +3585,7 @@ const struct flashchip flashchips[] = {
 		.unlock		= spi_disable_blockprotect,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read,
-		.voltage        = {2700, 3600},
+		.voltage	= {2700, 3600},
 	},
 
 	{
@@ -3620,7 +3620,7 @@ const struct flashchip flashchips[] = {
 		.unlock		= spi_disable_blockprotect,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read,
-		.voltage        = {2700, 3600},
+		.voltage	= {2700, 3600},
 	},
 
 	{
@@ -4014,7 +4014,7 @@ const struct flashchip flashchips[] = {
 		.unlock		= spi_disable_blockprotect,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read,
-		.voltage        = {2700, 3600},
+		.voltage	= {2700, 3600},
 	},
 
 	{
@@ -4051,7 +4051,7 @@ const struct flashchip flashchips[] = {
 		.unlock		= spi_disable_blockprotect,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read,
-		.voltage        = {2700, 3600},
+		.voltage	= {2700, 3600},
 	},
 
 	{
@@ -4178,7 +4178,7 @@ const struct flashchip flashchips[] = {
 		.page_size	= 256,
 		/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42 */
 		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP,
-		.tested		= TEST_UNTESTED,
+		.tested		= TEST_OK_PREW,
 		.probe		= probe_spi_rdid,
 		.probe_timing	= TIMING_ZERO,
 		.block_erasers	=
@@ -5032,7 +5032,7 @@ const struct flashchip flashchips[] = {
 		.total_size	= 16384,
 		.page_size	= 256,
 		.feature_bits	= FEATURE_WRSR_WREN,
-		.tested		= TEST_UNTESTED,
+		.tested		= TEST_OK_PROBE,
 		.probe		= probe_spi_rdid,
 		.probe_timing	= TIMING_ZERO,
 		.block_erasers	=
@@ -7044,7 +7044,7 @@ const struct flashchip flashchips[] = {
 		.total_size	= 384,
 		.page_size	= 64 * 1024,
 		.feature_bits	= FEATURE_REGISTERMAP | FEATURE_EITHER_RESET,
-		.tested		= TEST_OK_PR,
+		.tested		= TEST_OK_PREW,
 		.probe		= probe_jedec,
 		.probe_timing	= 1,		/* 150 ns */
 		.block_erasers	=
@@ -8060,29 +8060,29 @@ const struct flashchip flashchips[] = {
 		.voltage	= {2700, 3600},
 	},
 
-        {
-                .vendor         = "ST",
-                .name           = "M29W512B",
+	{
+		.vendor		= "ST",
+		.name		= "M29W512B",
 		.bustype	= BUS_PARALLEL,
-                .manufacture_id = ST_ID,
-                .model_id       = ST_M29W512B,
-                .total_size     = 64,
-                .page_size      = 64 * 1024,
-                .feature_bits   = FEATURE_ADDR_2AA | FEATURE_EITHER_RESET,
+		.manufacture_id = ST_ID,
+		.model_id	= ST_M29W512B,
+		.total_size	= 64,
+		.page_size	= 64 * 1024,
+		.feature_bits	= FEATURE_ADDR_2AA | FEATURE_EITHER_RESET,
 		.tested		= TEST_OK_PRE,
-                .probe          = probe_jedec,
-                .probe_timing   = TIMING_ZERO,
-                .block_erasers  =
-                {
-                        {
-                                .eraseblocks = { {64 * 1024, 1} },
-                                .block_erase = erase_chip_block_jedec,
-                        }
-                },
-                .write          = write_jedec_1,
-                .read           = read_memmapped,
+		.probe		= probe_jedec,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = { {64 * 1024, 1} },
+				.block_erase = erase_chip_block_jedec,
+			}
+		},
+		.write		= write_jedec_1,
+		.read		= read_memmapped,
 		.voltage	= {2700, 3600},
-        },
+	},
 
 	{
 		.vendor		= "ST",
@@ -9476,7 +9476,7 @@ const struct flashchip flashchips[] = {
 		.total_size	= 256,
 		.page_size	= 128,
 		.feature_bits	= FEATURE_EITHER_RESET,
-		.tested		= TEST_OK_PR,
+		.tested		= TEST_OK_PREW,
 		.probe		= probe_jedec,
 		.probe_timing	= 10,
 		.block_erasers	=
@@ -9721,6 +9721,21 @@ const struct flashchip flashchips[] = {
 		.read		= NULL,
 	},
 
+	{
+		.vendor		= "Winbond",
+		.name		= "unknown Winbond (ex Nexcom) SPI chip",
+		.bustype	= BUS_SPI,
+		.manufacture_id	= WINBOND_NEX_ID,
+		.model_id	= GENERIC_DEVICE_ID,
+		.total_size	= 0,
+		.page_size	= 256,
+		.tested		= TEST_BAD_PREW,
+		.probe		= probe_spi_rdid,
+		.probe_timing	= TIMING_ZERO,
+		.write		= NULL,
+		.read		= NULL,
+	},
+
 	{
 		.vendor		= "Generic",
 		.name		= "unknown SPI chip (RDID)",

flashrom.8

@@ -291,8 +291,9 @@ contents (using
 .BR \-r )
 and store it to a medium outside of your computer, like
 a USB drive or a network share. If you needed to run the board enable code
-already for probing, use it for reading too. Now you can try to write the
-new image. You should enable the board enable code in any case now, as it
+already for probing, use it for reading too.
+If reading succeeds and the contens of the read file look legit you can try to write the new image.
+You should enable the board enable code in any case now, as it
 has been written because it is known that writing/erasing without the board
 enable is going to fail. In any case (success or failure), please report to
 the flashrom mailing list, see below.
@@ -326,7 +327,7 @@ report so we can diagnose the problem.
 .B Intel chipsets
 .sp
 If you have an Intel chipset with an ICH8 or later southbridge with SPI flash
-attached, and if a valid descriptor was written to it (e.g. by the vendor), the
+attached, and if a valid descriptor was written to it (e.g.\& by the vendor), the
 chipset provides an alternative way to access the flash chip(s) named
 .BR "Hardware Sequencing" .
 It is much simpler than the normal access method (called
@@ -341,7 +342,7 @@ syntax where
 .BR auto ", " swseq " or " hwseq .
 By default
 .RB "(or when setting " ich_spi_mode=auto )
-the module tries to use swseq and only activates hwseq if need be (e.g. if
+the module tries to use swseq and only activates hwseq if need be (e.g.\& if
 important opcodes are inaccessible due to lockdown; or if more than one flash
 chip is attached). The other options (swseq, hwseq) select the respective mode
 (if possible).
@@ -482,7 +483,7 @@ the
 .sp
 syntax where
 .B size
-is the number of bytes (min. 1, max. 256).
+is the number of bytes (min.\& 1, max.\& 256).
 .sp
 Example:
 .sp
@@ -498,7 +499,7 @@ flash chip, you can specify a blacklist of SPI commands with the
 syntax where
 .B commandlist
 is a list of two-digit hexadecimal representations of
-SPI commands. If commandlist is e.g. 0302, flashrom will behave as if the SPI
+SPI commands. If commandlist is e.g.\& 0302, flashrom will behave as if the SPI
 controller refuses to run command 0x03 (READ) and command 0x02 (WRITE).
 commandlist may be up to 512 characters (256 commands) long.
 Implementation note: flashrom will detect an error during command execution.
@@ -514,7 +515,7 @@ you can specify an ignorelist of SPI commands with the
 syntax where
 .B commandlist
 is a list of two-digit hexadecimal representations of
-SPI commands. If commandlist is e.g. 0302, the emulated flash chip will ignore
+SPI commands. If commandlist is e.g.\& 0302, the emulated flash chip will ignore
 command 0x03 (READ) and command 0x02 (WRITE).  commandlist may be up to 512
 characters (256 commands) long.
 Implementation note: flashrom won't detect an error during command execution.
@@ -723,7 +724,7 @@ is installed in your system, you have to specify the PCI address of the card
 you want to use with the
 .B pci=
 parameter as explained in the
-.B nic3com
+.B nic3com et al.\& 
 section above.
 .sp
 More information about the hardware is available at
@@ -828,11 +829,11 @@ Many of the developers communicate via the
 IRC channel on
 .BR chat.freenode.net .
 You are welcome to join and ask questions, send us bug and success reports there
-too. Please provide a way to contact you later (e.g. a mail address) and be
+too. Please provide a way to contact you later (e.g.\& a mail address) and be
 patient if there is no immediate reaction. Also, we provide a pastebin service
 at
 .B http://paste.flashrom.org
-that is very useful when you want to share logs etc. without spamming the
+that is very useful when you want to share logs etc.\& without spamming the
 channel.
 .SS
 .B Laptops
@@ -853,7 +854,7 @@ One-time programmable (OTP) memory and unique IDs
 .sp
 Some flash chips contain OTP memory often denoted as "security registers".
 They usually have a capacity in the range of some bytes to a few hundred
-bytes and can be used to give devices unique IDs etc. flashrom is not able
+bytes and can be used to give devices unique IDs etc.  flashrom is not able
 to read or write these memories and may therefore not be able to duplicate a
 chip completely. For chip types known to include OTP memories a warning is
 printed when they are detected.

flashrom.c

@@ -631,16 +631,6 @@ out_free:
  * erasing. This is only possible if all chunks of size @gran are either kept
  * as-is or changed from an all-ones state to any other state.
  *
- * The following write granularities (enum @gran) are known:
- * - 1 bit. Each bit can be cleared individually.
- * - 1 byte. A byte can be written once. Further writes to an already written
- *   byte cause the contents to be either undefined or to stay unchanged.
- * - 128 bytes. If less than 128 bytes are written, the rest will be
- *   erased. Each write to a 128-byte region will trigger an automatic erase
- *   before anything is written. Very uncommon behaviour and unsupported by
- *   this function.
- * - 256 bytes. If less than 256 bytes are written, the contents of the
- *   unwritten bytes are undefined.
  * Warning: This function assumes that @have and @want point to naturally
  * aligned regions.
  *

ichspi.c

@@ -1689,7 +1689,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
 		}
 
 		tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR);
-		msg_pdbg("0x08: 0x%08x (FADDR)\n", tmp);
+		msg_pdbg2("0x08: 0x%08x (FADDR)\n", tmp);
 
 		if (desc_valid) {
 			tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP);
@@ -1704,6 +1704,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
 				ich_spi_rw_restricted |= ich9_handle_frap(tmp, i);
 		}
 
+		/* Handle PR registers */
 		for (i = 0; i < 5; i++) {
 			/* if not locked down try to disable PR locks first */
 			if (!ichspi_lock)

internal.c

@@ -344,9 +344,6 @@ int internal_init(void)
 		return 1;
 	}
 
-	/* Even if chipset init returns an error code, we don't want to abort.
-	 * The error code might have been a warning only.
-	 */
 #if defined(__i386__) || defined(__x86_64__) || defined (__mips)
 	register_par_programmer(&par_programmer_internal, internal_buses_supported);
 	return 0;

layout.c

@@ -78,7 +78,7 @@ int read_romlayout(char *name)
 		tstr1 = strtok(tempstr, ":");
 		tstr2 = strtok(NULL, ":");
 		if (!tstr1 || !tstr2) {
-			msg_gerr("Error parsing layout file.\n");
+			msg_gerr("Error parsing layout file. Offending string: \"%s\"\n", tempstr);
 			fclose(romlayout);
 			return 1;
 		}

spi.c

@@ -152,6 +152,7 @@ uint32_t spi_get_valid_read_addr(struct flashctx *flash)
 #if CONFIG_INTERNAL == 1
 #if defined(__i386__) || defined(__x86_64__)
 	case SPI_CONTROLLER_ICH7:
+	case SPI_CONTROLLER_ICH9:
 		/* Return BBAR for ICH chipsets. */
 		return ichspi_bbar;
 #endif