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If the JEDEC Toggle Bit algorithm needs more than 2^20 loops, it is a
good sign we should have used delays between toggle bit reads.

Tell the user about this. 2^20 loops need roughly a second depending on
flash bus speed. One reason for excessive loops can be a slow operation
like erase.

The Winbond W39V040C requires a 50 ms delay between toggle bit reads
during erase according to the datasheet. Turns out a 2 ms delay is
sufficient. Use a safety factor of 4 and default all erase operations
to 8 ms delay between toggle reads. This is short enough not to have
a substantial negative impact on erase times, and should improve
reliability.

This patch addresses the excessive toggle behaviour (observed on some
non-Winbond chips) and the toggle delay requirement (Winbond W39V040C).

Corresponding to flashrom svn r807.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Javier Ortega Conde (aka Malkavian) <malkavian666@gmail.com>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>