• Carl-Daniel Hailfinger's avatar
    Add infrastructure to check the maximum supported flash size of chipsets and mainboards · 115d390f
    Carl-Daniel Hailfinger authored
    
    The rationale is to warn users when they, for example, try to flash
    a 512KB parallel flash chip but their chipset only supports 256KB,
    or they try to flash 512KB and the chipset _does_ theoretically
    support 512KB but their special board doesn't wire all address lines
    and thus supports only 256 KB ROM chips at maximum.
    
    This has cost Uwe hours of debugging on some board already, until he
    figured out what was going on. We should try warn our users where
    possible about this.
    
    The chipset and the chip may have more than one bus in common (e.g.
    SB600 and Pm49* can both speak LPC+FWH) and on SB600/SB7x0/SB8x0 there
    are different limits for LPC and FWH. The only way to tell the user
    about the exact circumstances is to spew error messages per bus.
    
    The code will issue a warning during probe (which does fail for some
    chips if the size is too big) and abort before the first real
    read/write/erase action. If no action is specified, the warning is
    printed anyway.
    That way, a user can find out why probe might not have worked, and will
    be stopped before he/she gets incorrect results.
    
    Add a bitcount function to the infrastructure.
    
    Corresponding to flashrom svn r755.
    Signed-off-by: default avatarCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: default avatarUwe Hermann <uwe@hermann-uwe.de>
    115d390f
flash.h 24.6 KB