- 24 May, 2023 1 commit
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github-actions[bot] authored
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- 23 May, 2023 2 commits
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Miodrag Milanović authored
Fix importing parametrized VHDL entity
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Miodrag Milanovic authored
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- 22 May, 2023 4 commits
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Jannis Harder authored
Assign wires an smtoffset
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Jannis Harder authored
Add outputs before inputs to the sigmap in the AIGER backend.
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N. Engelhardt authored
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github-actions[bot] authored
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- 21 May, 2023 1 commit
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CORRADI Quentin authored
genvar declaration cannot take an initial value when declared as a module_or_generate_item_declaration. Correct this test so that it doesn't fail unexpectedly if Yosys aligns with the standard.
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- 18 May, 2023 3 commits
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Jannis Harder authored
When assigning values to input ports of nested modules in cosimulation, sim needs to find the actual driver of the signal to perform the assignment. The existing code didn't handle unconnected inputs in that scenario.
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Jannis Harder authored
While not setting the smtoffset here was clearly a bug, I think using `chunk.offset` only worked incidentally. The `smtoffset` is an offset into the `smtname, smtid` pair (here `"", idcounter`) which corresponds to the smt bitvector `stringf("%s#%d", get_id(module), idcounter)` which contains all the chunks this loop is iterating over. Thus using an incrementing `smtoffset` (like the `$ff`/`$dff` case above already does) should be the correct fix.
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github-actions[bot] authored
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- 17 May, 2023 5 commits
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Krystine Sherwin authored
Wires weren't being assigned an smtoffset value so when generating a yosys witness trace it would also use an offset of 0. Not sure if this has any other effects, but it fixes the bug I was having. @jix could you take a look at this?
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Miodrag Milanovic authored
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Miodrag Milanović authored
[YOSYS-2525] fix read_liberty newline handling #2525
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Muthiah Annamalai (முத்து அண்ணாமலை) authored
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Muthu Annamalai authored
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- 15 May, 2023 1 commit
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Miodrag Milanović authored
[YOSYS] Issue #3498 - Fix Synopsys style unquoted Liberty style
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- 10 May, 2023 2 commits
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Kamil Rakoczy authored
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
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github-actions[bot] authored
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- 09 May, 2023 7 commits
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Muthiah Annamalai (முத்து அண்ணாமலை) authored
Allow Liberty canonical identifier including double quotes in if-body and pass-through for Synopsys-style unquoted identifiers issue#3498 Co-authored-by: Aki <201479+lethalbit@users.noreply.github.com>
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Miodrag Milanović authored
gowin: Add all the primitives.
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Miodrag Milanović authored
gowin: Fix X output of $alu techmap
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Miodrag Milanović authored
Updated the `plugin` command to better handle paths
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Miodrag Milanovic authored
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Miodrag Milanovic authored
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github-actions[bot] authored
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- 08 May, 2023 4 commits
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N. Engelhardt authored
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N. Engelhardt authored
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N. Engelhardt authored
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Krystine Sherwin authored
Writeback of simulation state into initial state was only working for `run()` and `run_cosim_fst()`. This change moves the writeback into the `write_output_files()` function so that all simulation modes work with the writeback option.
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- 07 May, 2023 1 commit
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Muthu Annamalai authored
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- 06 May, 2023 1 commit
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YRabbit authored
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- 05 May, 2023 5 commits
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Miodrag Milanović authored
Synthesizable properties
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Muthu Annamalai authored
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Muthu Annamalai authored
- newlines can be allowed in function parsing
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YRabbit authored
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github-actions[bot] authored
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- 04 May, 2023 2 commits
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Jannis Harder authored
Handling of attributes for struct / union variables
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Dag Lem authored
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- 03 May, 2023 1 commit
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Dag Lem authored
(* nowrshmsk *) on a struct / union variable now affects dynamic bit slice assignments to members of the struct / union. (* nowrshmsk *) can in some cases yield significant resource savings; the combination of pipeline shifting and indexed writes is an example of this. Constructs similar to the one below can benefit from (* nowrshmsk *), and in addition it is no longer necessary to split out the shift assignments on separate lines in order to avoid the error message "ERROR: incompatible mix of lookahead and non-lookahead IDs in LHS expression." always_ff @(posedge clk) begin if (rotate) begin { v5, v4, v3, v2, v1, v0 } <= { v4, v3, v2, v1, v0, v5 }; if (res) begin v0.bytes <= '0; end else if (w) begin v0.bytes[addr] <= data; end end end
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