- 07 Oct, 2024 1 commit
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Raptor Engineering Development Team authored
This fixes failures observed after a cold reboot / watchdog timeout due to incorrect SFDP-incompatible settings remaining in the control registers.
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- 10 Apr, 2024 1 commit
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Raptor Engineering Development Team authored
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- 26 May, 2023 1 commit
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Raptor Engineering Development Team authored
This is useful on FPGAs where the additional PHY clock domains may overwhelm global clock routing resources.
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- 03 Apr, 2023 1 commit
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Raptor Engineering Development Team authored
Switch ADS795x driver idle clock polarity to 0 This fixes non-response of ADS795x devices under certain conditions
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- 17 Dec, 2022 1 commit
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Raptor Engineering Development Team authored
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- 15 Dec, 2022 1 commit
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Raptor Engineering Development Team authored
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- 14 Dec, 2022 1 commit
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Raptor Engineering Development Team authored
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- 16 May, 2022 1 commit
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Raptor Engineering Development Team authored
This resolves an issue where multiple instances of Tercel under LiteX could force the main sdrio clock off of global routing resources, causing a boot failure and general problems with the design.
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- 15 May, 2022 1 commit
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Raptor Engineering Development Team authored
When the external peripheral reset pulse length is short compared to the PHY clock period, the power on reset may be missed leaving the PHY in an undefined state. Synchronize the external peripheral reset signal into the PHY clock domain to avoid this potential issue.
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- 19 Apr, 2021 1 commit
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Raptor Engineering Development Team authored
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- 17 Mar, 2021 1 commit
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Raptor Engineering Development Team authored
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- 16 Mar, 2021 4 commits
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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