sim_16550_uart.vhdl · cc10f6b2892e2790726511d6d450405d27111fce · Kestrel Collaboration / Kestrel LiteX / pythondata-cpu-microwatt · GitLab

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uart: Add a simulation model for the 16550 compatible UART · cc10f6b2
Benjamin Herrenschmidt authored Jun 18, 2020
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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cc10f6b2

sim_16550_uart.vhdl 14.6 KB

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