• Paul Mackerras's avatar
    core: Remove fetch2 pipeline stage · b5a7dbb7
    Paul Mackerras authored
    
    
    The fetch2 stage existed primarily to provide a stash buffer for the
    output of icache when a stall occurred.  However, we can get the same
    effect -- of having the input to decode1 stay unchanged on a stall
    cycle -- by using the read enable of the BRAMs in icache, and by
    adding logic to keep the outputs unchanged on a clock cycle when
    stall_in = 1.  This reduces branch and interrupt latency by one
    cycle.
    Signed-off-by: default avatarPaul Mackerras <paulus@ozlabs.org>
    b5a7dbb7
Makefile 9.2 KB