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Kestrel Collaboration
Kestrel LiteX
migen
Commits
e7ed194d
Commit
e7ed194d
authored
6 years ago
by
Sebastien Bourdeauducq
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sayma_amc: do not constrain Ethernet clocks
parent
cfd6fcdd
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12 deletions
+2
-12
migen/build/platforms/sinara/sayma_amc.py
migen/build/platforms/sinara/sayma_amc.py
+2
-12
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migen/build/platforms/sinara/sayma_amc.py
View file @
e7ed194d
...
...
@@ -324,15 +324,5 @@ class Platform(XilinxPlatform):
self
,
"xcku040-ffva1156-1-c"
,
_io
,
_connectors
,
toolchain
=
"vivado"
)
def
do_finalize
(
self
,
fragment
):
XilinxPlatform
.
do_finalize
(
self
,
fragment
)
try
:
self
.
add_period_constraint
(
self
.
lookup_request
(
"eth_clocks"
).
rx
,
8.0
)
except
ConstraintError
:
pass
try
:
self
.
add_period_constraint
(
self
.
lookup_request
(
"eth_clocks"
).
tx
,
8.0
)
except
ConstraintError
:
pass
# We do not contrain Ethernet clocks here, since we do not know
# if they are RGMII (125MHz) or MII (25MHz)
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