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Kestrel Collaboration
Kestrel LiteX
migen
Commits
ddf52811
Commit
ddf52811
authored
7 years ago
by
Sebastien Bourdeauducq
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xilinx: fix Ultrascale IDDRE1 pin names
parent
714c79e5
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migen/build/xilinx/common.py
migen/build/xilinx/common.py
+4
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migen/build/xilinx/common.py
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ddf52811
...
...
@@ -202,10 +202,10 @@ class XilinxDDRInputImplKU(Module):
self
.
specials
+=
Instance
(
"IDDRE1"
,
p_DDR_CLK_EDGE
=
"SAME_EDGE_PIPELINED"
,
p_IS_C_INVERTED
=
0
,
i_
d
=
i
,
o_
q
1
=
o1
,
o_
q
2
=
o2
,
i_
c
=
clk
,
i_
cb
=~
clk
,
i_
r
=
0
i_
D
=
i
,
o_
Q
1
=
o1
,
o_
Q
2
=
o2
,
i_
C
=
clk
,
i_
CB
=~
clk
,
i_
R
=
0
)
...
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