1. 08 Aug, 2021 3 commits
  2. 05 Aug, 2021 2 commits
  3. 04 Aug, 2021 2 commits
  4. 03 Aug, 2021 1 commit
  5. 30 Jul, 2021 2 commits
  6. 29 Jul, 2021 1 commit
  7. 28 Jul, 2021 1 commit
    • Andrzej Głąbek's avatar
      drivers: i2s: Add support for nRF I2S peripherals · 32da1078
      Andrzej Głąbek authored
      
      Add a shim that allows using the nrfx I2S driver via the Zephyr API.
      Add also missing devicetree nodes representing the I2S peripherals
      in the nRF52 Series SoCs.
      Extend the "nordic,nrf-i2s" binding with a new property that allows
      specifying the clock source to be used by the I2S peripheral (so that
      it is possible to use HFXO for better accurracy of the peripheral clock
      or, in the nRF53 Series SoCs, to use the dedicated audio oscillator).
      Signed-off-by: default avatarAndrzej Głąbek <andrzej.glabek@nordicsemi.no>
      32da1078
  8. 22 Jul, 2021 1 commit
  9. 21 Jul, 2021 4 commits
  10. 19 Jul, 2021 1 commit
  11. 17 Jul, 2021 1 commit
    • Carlo Caione's avatar
      drivers: syscon: Add generic syscon API · bc305984
      Carlo Caione authored
      
      A syscon device is a device managing a memory region containing a set of
      registers that are not cohesive enough to represent as any specific type
      of device. We need a driver for that because several other drivers could
      use the same region at the same time and we need to io-map the region at
      boot for MMU enabled platforms.
      Signed-off-by: default avatarCarlo Caione <ccaione@baylibre.com>
      bc305984
  12. 16 Jul, 2021 1 commit
  13. 15 Jul, 2021 1 commit
  14. 14 Jul, 2021 1 commit
  15. 13 Jul, 2021 1 commit
    • Thomas Stranger's avatar
      dts: arm: introduce seeed lora-e5 module · 15d8f1ea
      Thomas Stranger authored
      
      This commit adds the dts definitons for the seeed lora-e5 module.
      Additionally I add myself as codeowner for the new dts/arm/seeed
      directory.
      
      This module packages a stm32wle5jc Sub-GHz Wireless Soc,
      together with a 32MHz TCXO, a 32.768KHz crystal oscillator, and
      power and RF circuitry.
      
      With the introduction of lora support definitions for the radio
      will be added in a future commit.
      Signed-off-by: default avatarThomas Stranger <thomas.stranger@outlook.com>
      15d8f1ea
  16. 08 Jul, 2021 1 commit
  17. 02 Jul, 2021 1 commit
  18. 01 Jul, 2021 1 commit
  19. 28 Jun, 2021 1 commit
  20. 24 Jun, 2021 1 commit
  21. 23 Jun, 2021 1 commit
  22. 22 Jun, 2021 1 commit
  23. 18 Jun, 2021 3 commits
  24. 15 Jun, 2021 1 commit
  25. 12 Jun, 2021 1 commit
  26. 07 Jun, 2021 1 commit
  27. 18 May, 2021 1 commit
    • Bob Recny's avatar
      boards: arm: Modify BMD-345-EVAL support · 8039ab48
      Bob Recny authored
      
      Modify support for u-blox BMD-345-EVAL which uses the nRF52840
      and a Skyworks RFX2411 FEM.
      
      These edits follow the naming cnoventions that is used
      with the other u-blox EVKs recently added, or in progress
      
      This board is similar to the nRF52840dk_nrf52840 with the
      addition of a FEM. Four Arduino GPIO pins have been
      reassigned to the PA_LNA control pins.
      
      u-blox would prefer to use this naming convention to match
      other BMD-3xx-EVAL and EVK-NINA-Bx boards recently submitted.
      
      Tested with blinky, button, and Bluetooth peripheral_hr
      Checking dts files
      Updated CODEOWNERS to rename bmd_345_eval to ubx_bmd345eval_nrf52840
      Added CMakeLists.txt, updated board.c
      Signed-off-by: default avatarBob Recny <bob.recny@u-blox.com>
      8039ab48
  28. 11 May, 2021 1 commit
  29. 08 May, 2021 1 commit
    • Carlo Caione's avatar
      cache: Introduce external cache controller system support · e2333269
      Carlo Caione authored
      
      The cache API currently shipped in Zephyr is assuming that the cache
      controller is always on-core thus managed at the arch level. This is not
      always the case because many SoCs rely on external cache controllers as
      a peripheral external to the core (for example PL310 cache controller
      and the L2Cxxx family). In some cases you also want a single driver to
      control a whole set of cache controllers.
      
      Rework the cache code introducing support for external cache
      controllers.
      Signed-off-by: default avatarCarlo Caione <ccaione@baylibre.com>
      e2333269
  30. 07 May, 2021 1 commit
    • Andy Ross's avatar
      drivers/timer: Add x86 APIC TSC_DEADLINE driver · 662b0bf7
      Andy Ross authored
      
      Modern hardware all supports a TSC_DEADLINE mode for the APIC timer,
      where the same GHz-scale 64 bit TSC used for performance monitoring
      becomes the free-running counter used for cpu-local timer interrupts.
      Being a free running counter that does not need to be reset, it will
      not lose time in an interrupt.  Being 64 bit, it needs no rollover or
      clamping logic in the driver when presented with a 32 bit tick count.
      Being a proper comparator, it will correctly trigger interrupts for
      times set "in the past" and thus needs no minimum/clamping logic.  The
      counter is synchronized across the system architecturally (modulo one
      burp where firmware likes to change the adjustment value) so usage is
      SMP-safe by default.  Access to the 64 bit counter and comparator
      value are single-instruction atomics even on 32 bit systems, so it
      beats even the RISC-V machine timer in complexity (which was our
      reigning champ for "simplest timer driver").
      
      Really this is just ideal for Zephyr.  So rather than try to add
      support for it to the existing APIC driver and increase complexity,
      make this a new standalone driver instead.  All modern hardware has
      what it needs.  The sole gotcha is that it's not easily emulatable
      (qemu supports it only under kvm where they can freeload on the host
      TSC) so it can be exercised only on hardware platforms right now.
      Signed-off-by: default avatarAndy Ross <andrew.j.ross@intel.com>
      662b0bf7