- 27 Apr, 2021 3 commits
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Daniel Leung authored
Due to the use of gperf to generate hash table for kobjects, the addresses of these kobjects cannot change during the last few phases of linking (especially between zephyr_prebuilt.elf and zephyr.elf). Because of this, the gperf generated data needs to be placed at the end of memory to avoid pushing symbols around in memory. This prevents moving these generated blocks to earlier sections, for example, pinned data section needed for demand paging. So create placeholders for use in intermediate linking to reserve space for these generated blocks. Due to uncertainty on the size of these blocks, more space is being reserved which could result in wasted space. Though, this retains the use of hash table for faster lookup. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
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Carlo Caione authored
Add support for the FVP Base RevC 2xAEMv8A board to be emulated using the same FVP. For now the virtual platform is only exposing one core and the basic set of peripherals (GICv3, ARM arch timer, PL011, etc...). INFO - Total complete: 256/ 256 100% skipped: 933, failed: 0 Signed-off-by: Carlo Caione <ccaione@baylibre.com>
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Erwan Gouriou authored
Add @galak as codeowner for dts/common Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
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- 22 Apr, 2021 7 commits
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Kumar Gala authored
Move emul.h out of the top level include/ dir into include/drivers/emul.h and deprecated the old location. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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Jiafei Pan authored
1. add a seperate 2 cores SMP board configuration to run in Jailhouse inmate Cell, root Cell Linux will use Core0 and Core1, Zephyr will run on Core2 and Core3. 2. Refine the code of dts, move SoC common dts nodes into dtsi fiel in dts/arm64/nxp/ directory. 3. Add myself to be code owner of directory dts/arm64/nxp/. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
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Julien Massot authored
Add GPIO controller driver that can be found on Renesas RCar gen3 soc series. Controller can handle up to 32 GPIOs per banks. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
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Julien Massot authored
Compare Match Timer is a 32 bit compare match timer that can be found on various Renesas R-Car SoC. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
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Julien Massot authored
Clock Pulse Generator, Module Standby Software Reset, are registers presents in Renesas Gen3 SoC series. MSSR is used to supply clock to the different modules, shuch as timer, or UART, it's also possible to issue a reset the different module. CPG registers allow to get the rate or to set some divider like for the CAN clock. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
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Julien Massot authored
Add basic configuration for H3ULCB, just enough to see the Zephyr boot banner on the ram console. This configuration make use of the Cortex-R7 present on r8a977951 SoC. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
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Julien Massot authored
Most of the Renesas RCar Gen3 based SoC contains a Cortex R7 processor. This processor has access to the same memory mapped devices than the Cortex-A5x cores. - CPU operates upto 800MHz - Can use ram area from 0x40040000 to 0x42000000 - Has 512 interrupts on GIC-400 compliant with Arm GICv2 Add support for r8a77951 as first SoC of this series which is also known as H3 ES2.0 and is present present on different boards such as Salvator and R-Car Starter Kit(H3ulcb). This first SoC definition is just enough to print Hello World in a ram console. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
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- 20 Apr, 2021 1 commit
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Anas Nashif authored
path updates after moving directories. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
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- 19 Apr, 2021 1 commit
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Guillaume Paquet authored
Add rak4631 board from RAKWireless based on nrf52840 and SX1262. Board Documentation is completed Signed-off-by: Guillaume Paquet <guillaume.paquet@smile.fr>
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- 13 Apr, 2021 5 commits
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Jaxson Han authored
Add essential files to create a new board. Enable arch timer, uart, multi-threading. Set memory map for flash and sram. The new board name is fvp_baser_aemv8r with the fvp_aemv8r_aarch64 soc. Signed-off-by: Jaxson Han <jaxson.han@arm.com>
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Jaxson Han authored
Armv8-R AArch64 MPU can support a maximum 16 memory regions, and the actual region number can be retrieved from the system register(MPUIR) during MPU initialization. Current MPU driver only suppots EL1. Signed-off-by: Haibo Xu <haibo.xu@arm.com> Signed-off-by: Jaxson Han <jaxson.han@arm.com>
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Jaxson Han authored
According to Armv8-R64 Spec, MPU related meta data(region base/limit) is 64 bits. So we need to re-define MPU related data structure here. Signed-off-by: Haibo Xu <haibo.xu@arm.com> Signed-off-by: Jaxson Han <jaxson.han@arm.com>
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Jaxson Han authored
Add armv8-r dtsi. Add dts binding yaml file for cortex-R82. Signed-off-by: Jaxson Han <jaxson.han@arm.com>
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Jaxson Han authored
Add essential files to create a new soc. Introduce a new type of soc series named fvp_aemv8r. Add a new soc named fvp_aemv8r_aarch64. Signed-off-by: Jaxson Han <jaxson.han@arm.com>
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- 09 Apr, 2021 1 commit
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Jiafei Pan authored
Add myself to be NXP Layserscape SoC and LS1046A board code-owner. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
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- 08 Apr, 2021 1 commit
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Gerard Marull-Paretas authored
It turns out that current known issues folder contains issues that are no longer valid or present. I have searched for some of the regex snippets listed but I have not been able to find any. Documentation was the last active user of the known-issues folder, but has moved to another solution. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
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- 02 Apr, 2021 1 commit
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Sun Amar authored
pwm driver + Kconfig and Cmake files for the efr32 soc family. Signed-off-by: Sun Amar <sun681@gmail.com>
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- 31 Mar, 2021 4 commits
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Carlo Caione authored
Fix the header guards, comments, github labeler, CODEOWNERS and MAINTAINERS files. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
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Lukasz Majewski authored
I would like to add myself as a co-maintainer for the ip_k66f board. Signed-off-by: Lukasz Majewski <lukma@denx.de>
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Maureen Helm authored
Add @mmahadevan108 and @dleach02 as collaborators for NXP SoCs, boards, and drivers. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
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Gerard Marull-Paretas authored
Move Sphinx related content to folders with underscore prefix. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
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- 25 Mar, 2021 1 commit
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Kumar Gala authored
Move ptp_clock.h out of the top level include/ dir into include/drivers/ptp_clock.h and deprecated the old location. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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- 23 Mar, 2021 3 commits
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Kumar Gala authored
Add initial support for the Cortex-M55 Core which is an implementation of the Armv8.1-M mainline architecture and includes support for the M‑profile Vector Extension (MVE). The support is based on the Cortex-M33 support that already exists in Zephyr. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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Johann Fischer authored
Add myself as disk subsystem code-owner Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
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Johann Fischer authored
Add common SDMMC_LOG_LEVEL and SDMMC_VOLUME_NAME. Initialize drivers at POST_KERNEL level. Update CODEOWNERS after sdmmc drivers relocation. Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
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- 22 Mar, 2021 1 commit
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Eugeniy Paltsev authored
Add @evgeniy-paltsev as an ARC part owner in addition to @abrodkin and @ruuddw, so he will be chosen as a reviewer automatically. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
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- 19 Mar, 2021 2 commits
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Hubert Miś authored
This patch includes initial support for FT800 display driver. It includes basic features. It can be easily extended with more FT800 display list and co-processor features. Signed-off-by: Hubert Miś <hubert.mis@gmail.com>
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Johann Fischer authored
Add myself as codeowner for modbus subsys. Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
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- 18 Mar, 2021 4 commits
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Dean Weiten authored
The Ronoth LoDev in an open source board which uses the AcSIP S76S. Signed-off-by: Dean Weiten <dmw@weiten.com>
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Dean Weiten authored
The AcSIP S76S is a STM32L073+SX1276+PA SoC which supports LoRa communications. Signed-off-by: Dean Weiten <dmw@weiten.com>
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Peter A. Bigot authored
I won't be supporting Zephyr for the foreseeable future, so remove my association with specific subsystems. Signed-off-by: Peter A. Bigot <pab@pabigot.com>
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Yonatan Schachter authored
This commit adds support for Silicon Labs EFR32FG13P (Flex Gecko) SoC. Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
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- 16 Mar, 2021 1 commit
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Gerson Fernando Budke authored
Introduce PSoC-6 pinctrl infraestructure and definitions. This add files to handle devicetree entries and following modifications: - add pinctrl bindings - update gpio bindings with pin-cells - add pinctrl node and move gpio nodes inside - declare pinctrl for current uart entries Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
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- 15 Mar, 2021 1 commit
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Martin Jäger authored
This new subsystem can be used to supervise individual threads. It is based on a regularly updated kernel timer, whose ISR is never actually called in regular system operation. An existing hardware watchdog can be used as an optional fallback if the task watchdog itself gets stuck. Signed-off-by: Martin Jäger <martin@libre.solar>
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- 11 Mar, 2021 1 commit
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Wojciech Tatarski authored
Add GPIO driver for QuickLogic EOS S3 SoC. Co-authored-by: Jan Kowalewski <jkowalewski@antmicro.com> Signed-off-by: Wojciech Tatarski <wtatarski@antmicro.com> Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
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- 09 Mar, 2021 1 commit
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Anas Nashif authored
Adapt to new location of samples. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
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- 08 Mar, 2021 1 commit
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Andrei Emeltchenko authored
I have not had time to work with USB recently, so removing myself from MAINTAINERS and CODEOWNERS for the USB subsystem. Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
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