Commit cf61cca3 authored by Francois Ramu's avatar Francois Ramu Committed by Christopher Friedt
Browse files

dts: arm: stm32 families redefines the dma compatibility


Each stm32 dma can be of V1 or V2 or V2bis type. Each type
has a dma-cell with specific nb of element. The feature and slot
properties are not required depending on the stm32 family.
Signed-off-by: default avatarFrancois Ramu <francois.ramu@st.com>
parent 9b1d21f0
......@@ -389,7 +389,7 @@
dma1: dma@40020000 {
compatible = "st,stm32-dma-v2";
#dma-cells = <4>;
#dma-cells = <3>;
reg = <0x40020000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
interrupts = <9 0 10 0 10 0 11 0 11 0>;
......
......@@ -70,7 +70,7 @@
dma2: dma@40020400 {
compatible = "st,stm32-dma-v2";
#dma-cells = <4>;
#dma-cells = <3>;
reg = <0x40020400 0x400>;
interrupts = <9 0 10 0 10 0 11 0 11 0 11 0
11 0 10 0 10 0 11 0 11 0 11 0>;
......
......@@ -317,8 +317,8 @@
};
dma1: dma@40020000 {
compatible = "st,stm32-dma-v2";
#dma-cells = <4>;
compatible = "st,stm32-dma-v2bis";
#dma-cells = <2>;
reg = <0x40020000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
......
......@@ -168,8 +168,8 @@
};
dma2: dma@40020400 {
compatible = "st,stm32-dma-v2";
#dma-cells = <4>;
compatible = "st,stm32-dma-v2bis";
#dma-cells = <2>;
reg = <0x40020400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
interrupts = < 56 0 57 0 58 0 59 0 60 0>;
......
......@@ -9,7 +9,8 @@
/ {
soc {
dma2: dma@40020400 {
compatible = "st,stm32-dma-v2";
compatible = "st,stm32-dma-v2bis";
#dma-cells = <2>;
reg = <0x40020400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
interrupts = <56 0 57 0 58 0 59 0 60 0>;
......
......@@ -398,8 +398,8 @@
};
dma1: dma@40020000 {
compatible = "st,stm32-dma-v2";
#dma-cells = <4>;
compatible = "st,stm32-dma-v2bis";
#dma-cells = <2>;
reg = <0x40020000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
......
......@@ -25,8 +25,8 @@
};
dma2: dma@40020400 {
compatible = "st,stm32-dma-v2";
#dma-cells = <4>;
compatible = "st,stm32-dma-v2bis";
#dma-cells = <2>;
reg = <0x40020400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
interrupts = <56 0 57 0 58 0 59 0 60 0>;
......
......@@ -25,8 +25,8 @@
};
dma2: dma@40020400 {
compatible = "st,stm32-dma-v2";
#dma-cells = <4>;
compatible = "st,stm32-dma-v2bis";
#dma-cells = <2>;
reg = <0x40020400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
interrupts = <56 0 57 0 58 0 59 0 60 0>;
......
......@@ -363,7 +363,7 @@
dma1: dma@40020000 {
compatible = "st,stm32-dma-v2";
#dma-cells = <4>;
#dma-cells = <3>;
reg = <0x40020000 0x400>;
interrupts = <9 0 10 0 10 0 11 0 11 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
......@@ -376,7 +376,7 @@
/* DMAMUX clock is enabled as long as DMA1 or DMA2 is enabled */
dmamux1: dmamux@40020800 {
compatible = "st,stm32-dmamux";
#dma-cells = <4>;
#dma-cells = <3>;
reg = <0x40020800 0x800>;
interrupts = <11 0>;
dma-channels = <5>;
......
......@@ -81,7 +81,7 @@
dma2: dma@40020400 {
compatible = "st,stm32-dma-v2";
#dma-cells = <4>;
#dma-cells = <3>;
reg = <0x40020400 0x400>;
interrupts = <11 0 11 0 11 0 11 0 11 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
......
......@@ -90,7 +90,7 @@
dma2: dma@40020400 {
compatible = "st,stm32-dma-v2";
#dma-cells = <4>;
#dma-cells = <3>;
reg = <0x40020400 0x400>;
interrupts = <11 0 11 0 11 0 11 0 11 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
......
......@@ -585,7 +585,7 @@
dma1: dma@40020000 {
compatible = "st,stm32-dma-v2";
#dma-cells = <4>;
#dma-cells = <3>;
reg = <0x40020000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
dma-offset = <0>;
......@@ -595,7 +595,7 @@
dma2: dma@40020400 {
compatible = "st,stm32-dma-v2";
#dma-cells = <4>;
#dma-cells = <3>;
reg = <0x40020400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
status = "disabled";
......@@ -604,7 +604,7 @@
dmamux1: dmamux@40020800 {
compatible = "st,stm32-dmamux";
#dma-cells = <4>;
#dma-cells = <3>;
reg = <0x40020800 0x400>;
interrupts = <94 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x4>;
......
......@@ -776,7 +776,7 @@
dmamux1: dmamux@40020800 {
compatible = "st,stm32-dmamux";
#dma-cells = <4>;
#dma-cells = <3>;
reg = <0x40020800 0x400>;
interrupts = <102 0>;
/* dmamux1 has no dedicated clock, so we enable dma1 clock */
......
......@@ -296,7 +296,7 @@
dma1: dma@40020000 {
compatible = "st,stm32-dma-v2";
#dma-cells = <4>;
#dma-cells = <3>;
reg = <0x40020000 0x400>;
interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
......
......@@ -368,7 +368,7 @@
dma1: dma@40020000 {
compatible = "st,stm32-dma-v2";
#dma-cells = <4>;
#dma-cells = <3>;
reg = <0x40020000 0x400>;
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
......@@ -379,7 +379,7 @@
dma2: dma@40020400 {
compatible = "st,stm32-dma-v2";
#dma-cells = <4>;
#dma-cells = <3>;
reg = <0x40020400 0x400>;
interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
......
......@@ -281,7 +281,7 @@
dmamux1: dmamux@40020800 {
compatible = "st,stm32-dmamux";
#dma-cells = <4>;
#dma-cells = <3>;
reg = <0x40020800 0x400>;
interrupts = <94 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x4>;
......
......@@ -377,7 +377,7 @@
dma1: dma@40020000 {
compatible = "st,stm32-dma-v2";
#dma-cells = <4>;
#dma-cells = <3>;
reg = <0x40020000 0x400>;
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
......@@ -389,7 +389,7 @@
dma2: dma@40020400 {
compatible = "st,stm32-dma-v2";
#dma-cells = <4>;
#dma-cells = <3>;
reg = <0x40020400 0x400>;
interrupts = <55 0 56 0 57 0 58 0 59 0 60 0 61 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
......@@ -401,7 +401,7 @@
dmamux1: dmamux@40020800 {
compatible = "st,stm32-dmamux";
#dma-cells = <4>;
#dma-cells = <3>;
reg = <0x40020800 0x400>;
interrupts = <62 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x4>;
......
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