Commit 36ba3d4a authored by Jan Kowalewski's avatar Jan Kowalewski Committed by Anas Nashif
Browse files

soc: add EOS S3 SoC


Add basic port for QuickLogic EOS S3 SoC.
Signed-off-by: default avatarJan Kowalewski <jkowalewski@antmicro.com>
parent ff0ff464
......@@ -42,6 +42,7 @@
/soc/arm/nuvoton/ @ssekar15
/soc/arm/nuvoton_npcx/ @MulinChao
/soc/arm/qemu_cortex_a53/ @carlocaione
/soc/arm/quicklogic_eos_s3/ @kowalewskijan @kgugala
/soc/arm/silabs_exx32/efr32mg21/ @l-alfred
/soc/arm/st_stm32/ @erwango
/soc/arm/st_stm32/stm32f4/ @idlethread
......
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
zephyr_sources(
soc.c
)
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_EOS_S3
bool
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
if SOC_EOS_S3
config SOC
default "quicklogic_eos_s3"
config NUM_IRQS
default 52
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 61440000
if SERIAL
config UART_PL011
default y
config UART_INTERRUPT_DRIVEN
default y
config UART_PL011_PORT0
default y
config UART_PL011_PORT1
default n
endif # SERIAL
endif # SOC_EOS_S3
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_EOS_S3
bool "QuickLogic EOS S3 SoC"
select ARM
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_HAS_ARM_MPU
select EOS_S3_HAL
/*
# Copyright (c) 2020 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>
/*
* Copyright (c) 2020 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <kernel.h>
#include <init.h>
#include <soc.h>
#include <soc_pinmap.h>
#include <arch/arm/aarch32/cortex_m/cmsis.h>
void eos_s3_lock_enable(void)
{
MISC_CTRL->LOCK_KEY_CTRL = MISC_LOCK_KEY;
}
void eos_s3_lock_disable(void)
{
MISC_CTRL->LOCK_KEY_CTRL = 1;
}
int eos_s3_io_mux(uint32_t pad_nr, uint32_t pad_cfg)
{
volatile uint32_t *p = (uint32_t *)IO_MUX_BASE;
if (pad_nr > EOS_S3_MAX_PAD_NR) {
return -EINVAL;
}
p += pad_nr;
*p = pad_cfg;
return 0;
}
static void eos_s3_cru_init(void)
{
/* Set desired frequency */
AIP->OSC_CTRL_0 |= AIP_OSC_CTRL_EN;
AIP->OSC_CTRL_0 &= ~AIP_OSC_CTRL_FRE_SEL;
OSC_SET_FREQ_INC(HSOSC_60MHZ);
while (!OSC_CLK_LOCKED()) {
;
}
/* Enable all clocks for every domain */
CRU->CLK_DIVIDER_CLK_GATING = (CLK_DIVIDER_A_CG | CLK_DIVIDER_B_CG
| CLK_DIVIDER_C_CG | CLK_DIVIDER_D_CG | CLK_DIVIDER_F_CG
| CLK_DIVIDER_G_CG | CLK_DIVIDER_H_CG | CLK_DIVIDER_I_CG
| CLK_DIVIDER_J_CG);
/* Turn off divisor for A0 domain */
CRU->CLK_CTRL_A_0 = 0;
/* Enable UART, WDT and TIMER peripherals */
CRU->C11_CLK_GATE = C11_CLK_GATE_PATH_0_ON;
/* Set divider for domain C11 to ~ 5.12MHz */
CRU->CLK_CTRL_D_0 = (CLK_CTRL_CLK_DIVIDER_ENABLE |
CLK_CTRL_CLK_DIVIDER_RATIO_12);
}
static int eos_s3_init(const struct device *arg)
{
uint32_t key;
ARG_UNUSED(arg);
/* Clocks setup */
eos_s3_lock_enable();
eos_s3_cru_init();
eos_s3_lock_disable();
SCnSCB->ACTLR |= SCnSCB_ACTLR_DISDEFWBUF_Msk;
/* Clear all interrupts */
INTR_CTRL->OTHER_INTR = 0xFFFFFF;
/* Enable UART interrupt */
INTR_CTRL->OTHER_INTR_EN_M4 = UART_INTR_EN_M4;
key = irq_lock();
NMI_INIT();
irq_unlock(key);
return 0;
}
SYS_INIT(eos_s3_init, PRE_KERNEL_1, 0);
/*
* Copyright (c) 2020 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC__H_
#define _SOC__H_
#include <sys/util.h>
#include <eoss3_dev.h>
#include <devicetree.h>
/* Available frequencies */
#define HSOSC_1MHZ 1024000
#define HSOSC_2MHZ (2*HSOSC_1MHZ)
#define HSOSC_3MHZ (3*HSOSC_1MHZ)
#define HSOSC_4MHZ (4*HSOSC_1MHZ)
#define HSOSC_5MHZ (5*HSOSC_1MHZ)
#define HSOSC_6MHZ (6*HSOSC_1MHZ)
#define HSOSC_8MHZ (8*HSOSC_1MHZ)
#define HSOSC_9MHZ (9*HSOSC_1MHZ)
#define HSOSC_10MHZ (10*HSOSC_1MHZ)
#define HSOSC_12MHZ (12*HSOSC_1MHZ)
#define HSOSC_15MHZ (15*HSOSC_1MHZ)
#define HSOSC_16MHZ (16*HSOSC_1MHZ)
#define HSOSC_18MHZ (18*HSOSC_1MHZ)
#define HSOSC_20MHZ (20*HSOSC_1MHZ)
#define HSOSC_21MHZ (21*HSOSC_1MHZ)
#define HSOSC_24MHZ (24*HSOSC_1MHZ)
#define HSOSC_27MHZ (27*HSOSC_1MHZ)
#define HSOSC_30MHZ (30*HSOSC_1MHZ)
#define HSOSC_32MHZ (32*HSOSC_1MHZ)
#define HSOSC_35MHZ (35*HSOSC_1MHZ)
#define HSOSC_36MHZ (36*HSOSC_1MHZ)
#define HSOSC_40MHZ (40*HSOSC_1MHZ)
#define HSOSC_45MHZ (45*HSOSC_1MHZ)
#define HSOSC_48MHZ (48*HSOSC_1MHZ)
#define HSOSC_54MHZ (54*HSOSC_1MHZ)
#define HSOSC_60MHZ (60*HSOSC_1MHZ)
#define HSOSC_64MHZ (64*HSOSC_1MHZ)
#define HSOSC_70MHZ (70*HSOSC_1MHZ)
#define HSOSC_72MHZ (72*HSOSC_1MHZ)
#define HSOSC_80MHZ (80*HSOSC_1MHZ)
#define OSC_CLK_LOCKED() (AIP->OSC_STA_0 & 0x1)
#define OSC_SET_FREQ_INC(FREQ) (AIP->OSC_CTRL_1 = ((FREQ / 32768) - 3) & 0xFFF)
#define OSC_GET_FREQ_INC() (((AIP->OSC_CTRL_1 & 0xFFF) + 3) * 32768)
#define EOS_S3_MAX_PAD_NR 45
void eos_s3_lock_enable(void);
void eos_s3_lock_disable(void);
int eos_s3_io_mux(uint32_t pad_nr, uint32_t pad_cfg);
#endif /* _SOC__H_ */
/*
* Copyright (c) 2020 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _QUICKLOGIC_EOS_S3_SOC_PINMAP_H_
#define _QUICKLOGIC_EOS_S3_SOC_PINMAP_H_
#include <soc.h>
/* Set UART TX to PAD44 */
#define UART_TXD_PAD44 (UART_TXD_SEL_PAD44 | PAD_CTRL_SEL_AO_REG \
| PAD_OEN_NORMAL | PAD_P_Z | PAD_SR_SLOW \
| PAD_E_4MA | PAD_REN_DISABLE | PAD_SMT_DISABLE)
/* Set UART RX to PAD45 */
#define UART_RXD_PAD45 (UART_RXD_SEL_PAD45 | PAD_CTRL_SEL_AO_REG \
| PAD_OEN_DISABLE | PAD_P_Z | PAD_SR_SLOW \
| PAD_E_4MA | PAD_REN_ENABLE | PAD_SMT_DISABLE)
#endif /* _QUICKLOGIC_EOS_S3_SOC_PINMAP_H_ */
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