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Jonathan Currier
pythondata-cpu-microwatt
Commits
ba766523
Commit
ba766523
authored
4 years ago
by
LiteX
Committed by
Travis CI User
4 years ago
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Merge commit '
13da4caa
'
parents
8746a258
13da4caa
Changes
5
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5 changed files
with
72 additions
and
61 deletions
+72
-61
pythondata_cpu_microwatt/vhdl/Makefile
pythondata_cpu_microwatt/vhdl/Makefile
+16
-11
pythondata_cpu_microwatt/vhdl/openocd/bscan_spi_xc7a200t.bit
pythondata_cpu_microwatt/vhdl/openocd/bscan_spi_xc7a200t.bit
+0
-0
pythondata_cpu_microwatt/vhdl/openocd/flash-arty
pythondata_cpu_microwatt/vhdl/openocd/flash-arty
+3
-1
pythondata_cpu_microwatt/vhdl/openocd/jtagspi.cfg
pythondata_cpu_microwatt/vhdl/openocd/jtagspi.cfg
+0
-47
pythondata_cpu_microwatt/vhdl/openocd/xilinx-xc7.cfg
pythondata_cpu_microwatt/vhdl/openocd/xilinx-xc7.cfg
+53
-2
No files found.
pythondata_cpu_microwatt/vhdl/Makefile
View file @
ba766523
GHDL
?=
ghdl
GHDLFLAGS
=
--std
=
08
--work
=
unisim
-frelaxed
GHDLFLAGS
=
--std
=
08
-frelaxed
CFLAGS
=
-O3
-Wall
GHDLSYNTH
?=
ghdl.so
...
...
@@ -54,12 +54,17 @@ soc_files = wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl
soc_sim_files
=
sim_console.vhdl sim_uart.vhdl sim_bram_helpers.vhdl
\
sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl
\
sim-unisim/BSCANE2.vhdl sim-unisim/BUFG.vhdl
\
sim-unisim/unisim_vcomponents.vhdl dmi_dtm_xilinx.vhdl
sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl
unisim_lib
=
sim-unisim/unisim-obj08.cf
unisim_lib_files
=
sim-unisim/BSCANE2.vhdl sim-unisim/BUFG.vhdl
\
sim-unisim/unisim_vcomponents.vhdl
$(unisim_lib)
:
$(unisim_lib_files)
ghdl
-i
--std
=
08
--work
=
unisim
--workdir
=
sim-unisim
$^
soc_sim_c_files
=
sim_vhpi_c.c sim_bram_helpers_c.c sim_console_c.c
\
sim_jtag_socket_c.c
soc_sim_obj_files
=
$(soc_sim_c_files:.c=.o)
comma
:=
,
soc_sim_link
=
$(
patsubst
%,-Wl
$(comma)
%,
$(soc_sim_obj_files)
)
...
...
@@ -68,8 +73,8 @@ core_tbs = multiply_tb divider_tb rotator_tb countzero_tb
soc_tbs
=
core_tb icache_tb dcache_tb dmi_dtm_tb wishbone_bram_tb
soc_dram_tbs
=
dram_tb core_dram_tb
$(soc_tbs)
:
%: $(core_files) $(soc_files) $(soc_sim_files) $(soc_sim_obj_files) %.vhdl
$(GHDL)
-c
$(GHDLFLAGS)
$(soc_sim_link)
$(core_files)
$(soc_files)
$(soc_sim_files)
$@
.vhdl
-e
$@
$(soc_tbs)
:
%: $(core_files) $(soc_files) $(soc_sim_files) $(soc_sim_obj_files)
$(unisim_lib)
%.vhdl
$(GHDL)
-c
$(GHDLFLAGS)
-Psim-unisim
$(soc_sim_link)
$(core_files)
$(soc_files)
$(soc_sim_files)
$@
.vhdl
-e
$@
$(core_tbs)
:
%: $(core_files) glibc_random.vhdl glibc_random_helpers.vhdl %.vhdl
$(GHDL)
-c
$(GHDLFLAGS)
$(core_files)
glibc_random.vhdl glibc_random_helpers.vhdl
$@
.vhdl
-e
$@
...
...
@@ -101,8 +106,8 @@ soc_dram_sim_obj_files = $(soc_sim_obj_files) sim_litedram_c.o
dram_link_files
=
-Wl
,obj_dir/Vlitedram_core__ALL.a
-Wl
,obj_dir/verilated.o
-Wl
,obj_dir/verilated_vcd_c.o
-Wl
,-lstdc++
soc_dram_sim_link
=
$(
patsubst
%,-Wl
$(comma)
%,
$(soc_dram_sim_obj_files)
)
$(dram_link_files)
$(soc_dram_tbs)
:
%: $(core_files) $(soc_dram_files) $(soc_dram_sim_files) $(soc_dram_sim_obj_files) %.vhdl
$(GHDL)
-c
$(GHDLFLAGS)
$(soc_dram_sim_link)
$(core_files)
$(soc_dram_files)
$(soc_dram_sim_files)
$@
.vhdl
-e
$@
$(soc_dram_tbs)
:
%: $(core_files) $(soc_dram_files) $(soc_dram_sim_files) $(soc_dram_sim_obj_files)
$(unisim_lib)
%.vhdl
$(GHDL)
-c
$(GHDLFLAGS)
-Psim-unisim
$(soc_dram_sim_link)
$(core_files)
$(soc_dram_files)
$(soc_dram_sim_files)
$@
.vhdl
-e
$@
endif
# Hello world
...
...
@@ -209,9 +214,9 @@ TAGS:
.PHONY
:
TAGS
_clean
:
rm
-f
*
.o
work-
*
cf unisim-
*
cf
$(all)
rm
-f
fpga/
*
.o fpga/
work-
*
cf
rm
-f
sim-unisim/
*
.o sim-unisim/
unisim-
*
cf
rm
-f
*
.o
*
.
cf
$(all)
rm
-f
fpga/
*
.o fpga/
*
.
cf
rm
-f
sim-unisim/
*
.o sim-unisim/
*
.
cf
rm
-f
litedram/extras/
*
.o
rm
-f
TAGS
rm
-f
scripts/mw_debug/
*
.o
...
...
This diff is collapsed.
Click to expand it.
pythondata_cpu_microwatt/vhdl/openocd/bscan_spi_xc7a200t.bit
0 → 100644
View file @
ba766523
File added
This diff is collapsed.
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pythondata_cpu_microwatt/vhdl/openocd/flash-arty
View file @
ba766523
...
...
@@ -23,7 +23,7 @@ def flash(config, flash_proxy, address, data, filetype="", set_qe=False):
parser
=
argparse
.
ArgumentParser
()
parser
.
add_argument
(
"file"
,
help
=
"file to write to flash"
)
parser
.
add_argument
(
"-a"
,
"--address"
,
help
=
"offset in flash"
,
type
=
lambda
x
:
int
(
x
,
0
),
default
=
0
)
parser
.
add_argument
(
"-f"
,
"--fpga"
,
help
=
"a35 or a
1
00"
,
default
=
"a35"
)
parser
.
add_argument
(
"-f"
,
"--fpga"
,
help
=
"a35
, a100
or a
2
00"
,
default
=
"a35"
)
parser
.
add_argument
(
"-t"
,
"--filetype"
,
help
=
"file type such as 'bin'"
,
default
=
""
)
args
=
parser
.
parse_args
()
...
...
@@ -31,6 +31,8 @@ if args.fpga.lower() == "a35":
proxy
=
"bscan_spi_xc7a35t.bit"
elif
args
.
fpga
.
lower
()
==
"a100"
:
proxy
=
"bscan_spi_xc7a100t.bit"
elif
args
.
fpga
.
lower
()
==
"a200"
:
proxy
=
"bscan_spi_xc7a200t.bit"
else
:
print
(
"error: specify a35 or a100 when flashing"
)
sys
.
exit
()
...
...
This diff is collapsed.
Click to expand it.
pythondata_cpu_microwatt/vhdl/openocd/jtagspi.cfg
View file @
ba766523
set _USER1 0x02
if { [info exists JTAGSPI_IR] } {
set _JTAGSPI_IR $JTAGSPI_IR
} else {
set _JTAGSPI_IR $_USER1
}
if { [info exists DR_LENGTH] } {
set _DR_LENGTH $DR_LENGTH
} else {
set _DR_LENGTH 1
}
if { [info exists TARGETNAME] } {
set _TARGETNAME $TARGETNAME
} else {
set _TARGETNAME $_CHIPNAME.proxy
}
if { [info exists FLASHNAME] } {
set _FLASHNAME $FLASHNAME
} else {
set _FLASHNAME $_CHIPNAME.spi
}
target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR $_DR_LENGTH
proc jtagspi_init {chain_id proxy_bit} {
# load proxy bitstream $proxy_bit and probe spi flash
global _FLASHNAME
pld load $chain_id $proxy_bit
reset halt
flash probe $_FLASHNAME
}
proc jtagspi_program {bin addr {type ""} } {
# write and verify binary file $bin at offset $addr
global _FLASHNAME
if { $type eq "" } {
flash write_image erase $bin $addr
flash verify_bank $_FLASHNAME $bin $addr
} else {
flash write_image erase $bin $addr $type
flash verify_bank $_FLASHNAME $bin $addr $type
}
}
This diff is collapsed.
Click to expand it.
pythondata_cpu_microwatt/vhdl/openocd/xilinx-xc7.cfg
View file @
ba766523
...
...
@@ -3,10 +3,61 @@ ftdi_vid_pid 0x0403 0x6010
ftdi_channel 0
ftdi_layout_init 0x00e8 0x60eb
reset_config none
adapter_khz 25000
source [find cpld/xilinx-xc7.cfg]
source openocd/jtagspi.cfg
adapter_khz 25000
# From jtagspi.cfg with modification to support
# specifying file type
set _USER1 0x02
if { [info exists JTAGSPI_IR] } {
set _JTAGSPI_IR $JTAGSPI_IR
} else {
set _JTAGSPI_IR $_USER1
}
if { [info exists DR_LENGTH] } {
set _DR_LENGTH $DR_LENGTH
} else {
set _DR_LENGTH 1
}
if { [info exists TARGETNAME] } {
set _TARGETNAME $TARGETNAME
} else {
set _TARGETNAME $_CHIPNAME.proxy
}
if { [info exists FLASHNAME] } {
set _FLASHNAME $FLASHNAME
} else {
set _FLASHNAME $_CHIPNAME.spi
}
target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR $_DR_LENGTH
proc jtagspi_init {chain_id proxy_bit} {
# load proxy bitstream $proxy_bit and probe spi flash
global _FLASHNAME
pld load $chain_id $proxy_bit
reset halt
flash probe $_FLASHNAME
}
proc jtagspi_program {bin addr {type ""} } {
# write and verify binary file $bin at offset $addr
global _FLASHNAME
if { $type eq "" } {
flash write_image erase $bin $addr
flash verify_bank $_FLASHNAME $bin $addr
} else {
flash write_image erase $bin $addr $type
flash verify_bank $_FLASHNAME $bin $addr $type
}
}
# end jtagspi.cfg
proc fpga_program {} {
global _CHIPNAME
...
...
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