Commit 2840ff69 authored by Jonathan Currier's avatar Jonathan Currier
Browse files

Bring Out the Reset address so it can be synth-time configurable

parent 75020a20
......@@ -12,6 +12,7 @@ entity core is
DISABLE_FLATTEN : boolean := false;
EX1_BYPASS : boolean := true;
ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
LOG_LENGTH : natural := 0
);
port (
......@@ -175,10 +176,9 @@ begin
alt_reset_d <= alt_reset;
end if;
end process;
fetch1_0: entity work.fetch1
generic map (
RESET_ADDRESS => (others => '0'),
RESET_ADDRESS => RESET_ADDRESS,
ALT_RESET_ADDRESS => ALT_RESET_ADDRESS
)
port map (
......
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