#!/usr/bin/env python3 # This file is Copyright (c) 2020 Fei Gao <feig@princeton.edu> # This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr> # This file is Copyright (c) 2020 David Shah <dave@ds0.me> # License: BSD import argparse from migen import * from litex_boards.platforms import alveo_u250 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litedram.modules import MTA18ASF2G72PZ from litedram.phy import usddrphy # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_pll4x = ClockDomain(reset_less=True) self.clock_domains.cd_clk500 = ClockDomain() # # # self.submodules.pll = pll = USMMCM(speedgrade=-2) self.comb += pll.reset.eq(0) pll.register_clkin(platform.request("clk300", 0), 300e6) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) pll.create_clkout(self.cd_clk500, 500e6, with_reset=False) self.specials += [ Instance("BUFGCE_DIV", name="main_bufgce_div", p_BUFGCE_DIVIDE=4, i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk), Instance("BUFGCE", name="main_bufgce", i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk), AsyncResetSynchronizer(self.cd_clk500, ~pll.locked), ] self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_clk500, cd_sys=self.cd_sys) # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = alveo_u250.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"), memtype = "DDR4", sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 500e6, cmd_latency = 1, is_rdimm = True) self.add_csr("ddrphy") self.add_constant("USDDRPHY_DEBUG") self.add_sdram("sdram", phy = self.ddrphy, module = MTA18ASF2G72PZ(sys_clk_freq, "1:4"), origin = self.mem_map["main_ram"], size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), l2_cache_reverse = True ) self.add_ram("firmware_ram", 0x20000000, 0x8000) # Build -------------------------------------------------------------------------------------------- def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Alveo U250") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() soc = BaseSoC(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build() if __name__ == "__main__": main()