#!/usr/bin/env python3 # This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr> # License: BSD import argparse from migen import * from litex_boards.platforms import nexys4ddr from litex.soc.cores.clock import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litedram.modules import MT47H64M16 from litedram.phy import s7ddrphy from liteeth.phy.rmii import LiteEthPHYRMII from liteeth.mac import LiteEthMAC # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys2x = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() self.clock_domains.cd_eth = ClockDomain() # # # self.submodules.pll = pll = S7MMCM(speedgrade=-1) self.comb += pll.reset.eq(~platform.request("cpu_reset")) pll.register_clkin(platform.request("clk100"), 100e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq) pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90) pll.create_clkout(self.cd_clk200, 200e6) pll.create_clkout(self.cd_eth, 50e6) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs): platform = nexys4ddr.Platform() # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size = integrated_rom_size, integrated_sram_size = 0x8000, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR2 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype = "DDR2", nphases = 2, sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") sdram_module = MT47H64M16(sys_clk_freq, "1:2") self.register_sdram(self.ddrphy, geom_settings = sdram_module.geom_settings, timing_settings = sdram_module.timing_settings) self.add_constant("MEMTEST_ADDR_SIZE", 0) # FIXME # EthernetSoC -------------------------------------------------------------------------------------- class EthernetSoC(BaseSoC): mem_map = { "ethmac": 0xb0000000, } mem_map.update(BaseSoC.mem_map) def __init__(self, **kwargs): BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs) self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), self.platform.request("eth")) self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk) # Build -------------------------------------------------------------------------------------------- def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Nexys4DDR") builder_args(parser) soc_sdram_args(parser) parser.add_argument("--sys-clk-freq", default=75e6, help="system clock frequency (default=75MHz)") parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") args = parser.parse_args() cls = EthernetSoC if args.with_ethernet else BaseSoC soc = cls(sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build() if __name__ == "__main__": main()