Commit febb5bce authored by Timothy Pearson's avatar Timothy Pearson

Test sytem for 8 bit Wishbone access

parent 0ecb8609
// Copyright 2020 Raptor Engineering, LLC
// Released under the terms of the two-clause BSD license
module test_wishbone_module(
// Wishbone signals
input wire wb_cyc,
input wire wb_stb,
input wire wb_we,
input wire [31:0] wb_addr,
input wire [7:0] wb_dat_w,
output wire [7:0] wb_dat_r,
output wire wb_ack,
output wire wb_err,
input wire peripheral_reset,
input wire peripheral_clock
);
reg wb_ack_reg = 0;
assign wb_ack = wb_ack_reg;
reg [7:0] wb_dat_r_reg = 0;
assign wb_dat_r = wb_dat_r_reg;
reg [7:0] wishbone_transfer_state = 0;
reg wb_data_cycle_type = 0;
reg [31:0] wb_address_reg = 0;
always @(posedge peripheral_clock) begin
if (peripheral_reset) begin
wb_ack_reg <= 0;
wishbone_transfer_state <= 0;
end else begin
case (wishbone_transfer_state)
0: begin
if (wb_cyc && wb_stb) begin
wb_data_cycle_type <= wb_we;
wb_address_reg <= wb_addr;
wishbone_transfer_state <= 1;
end
end
1: begin
wb_dat_r_reg <= (wb_address_reg[7:0] + 8'h80);
wb_ack_reg <= 1;
wishbone_transfer_state <= 2;
end
2: begin
wb_ack_reg <= 0;
wishbone_transfer_state <= 0;
end
endcase
end
end
endmodule
\ No newline at end of file
...@@ -15,6 +15,7 @@ from litex_boards.platforms import versa_ecp5 ...@@ -15,6 +15,7 @@ from litex_boards.platforms import versa_ecp5
from litex.build.lattice.trellis import trellis_args, trellis_argdict from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.cores.clock import * from litex.soc.cores.clock import *
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import * from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
...@@ -25,6 +26,25 @@ from litedram.phy import ECP5DDRPHY ...@@ -25,6 +26,25 @@ from litedram.phy import ECP5DDRPHY
from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
from litex.soc.interconnect import wishbone, stream
class TestModule(Module, AutoCSR):
def __init__(self, platform, endianness="big"):
self.bus = bus = wishbone.Interface(data_width=8, adr_width=32)
self.specials += Instance("test_wishbone_module",
i_wb_cyc = bus.cyc,
i_wb_stb = bus.stb,
i_wb_we = bus.we,
i_wb_addr = bus.adr,
i_wb_dat_w = bus.dat_w,
o_wb_dat_r = bus.dat_r,
o_wb_ack = bus.ack,
o_wb_err = bus.err,
i_peripheral_reset = ResetSignal('sys'),
i_peripheral_clock = ClockSignal('sys')
)
platform.add_source("rtl/test_wb_module.v")
# CRG ---------------------------------------------------------------------------------------------- # CRG ----------------------------------------------------------------------------------------------
class _CRG(Module): class _CRG(Module):
...@@ -73,6 +93,10 @@ class _CRG(Module): ...@@ -73,6 +93,10 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
mem_map = {
"testmodule": 0xc8000000,
}
mem_map.update(SoCCore.mem_map)
def __init__(self, sys_clk_freq=int(75e6), device="LFE5UM5G", with_ethernet=False, toolchain="trellis", **kwargs): def __init__(self, sys_clk_freq=int(75e6), device="LFE5UM5G", with_ethernet=False, toolchain="trellis", **kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain, device=device) platform = versa_ecp5.Platform(toolchain=toolchain, device=device)
...@@ -111,6 +135,15 @@ class BaseSoC(SoCCore): ...@@ -111,6 +135,15 @@ class BaseSoC(SoCCore):
self.add_csr("ethphy") self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy) self.add_ethernet(phy=self.ethphy)
# Test module
self.submodules.testmodule = TestModule(
platform = platform,
endianness = self.cpu.endianness)
self.add_csr("testmodule")
testmodule_size = 64*1024*1024
testmodule_region = SoCRegion(origin=self.mem_map.get("testmodule", None), size=testmodule_size, cached=False)
self.bus.add_slave(name="testmodule", slave=self.testmodule.bus, region=testmodule_region)
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser( self.submodules.leds = LedChaser(
pads = Cat(*[platform.request("user_led", i) for i in range(8)]), pads = Cat(*[platform.request("user_led", i) for i in range(8)]),
......
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