zcu104.py 4.36 KB
Newer Older
Piotr Binkowski's avatar
Piotr Binkowski committed
1
#!/usr/bin/env python3
Florent Kermarrec's avatar
Florent Kermarrec committed
2

Florent Kermarrec's avatar
Florent Kermarrec committed
3
# This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
Florent Kermarrec's avatar
Florent Kermarrec committed
4 5 6
# This file is Copyright (c) 2019 David Shah <dave@ds0.me>
# License: BSD

7
import os
Piotr Binkowski's avatar
Piotr Binkowski committed
8 9 10 11 12 13 14
import argparse

from migen import *

from litex_boards.platforms import zcu104

from litex.soc.cores.clock import *
15
from litex.soc.integration.soc_core import *
Piotr Binkowski's avatar
Piotr Binkowski committed
16 17
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
18
from litex.soc.cores.led import LedChaser
Jędrzej Boczar's avatar
Jędrzej Boczar committed
19
from litex.soc.cores.bitbang import I2CMaster
Piotr Binkowski's avatar
Piotr Binkowski committed
20

21
from litedram.modules import MTA4ATF51264HZ
Piotr Binkowski's avatar
Piotr Binkowski committed
22 23 24 25 26 27 28 29 30 31
from litedram.phy import usddrphy

# CRG ----------------------------------------------------------------------------------------------

class _CRG(Module):
    def __init__(self, platform, sys_clk_freq):
        self.clock_domains.cd_sys    = ClockDomain()
        self.clock_domains.cd_sys4x  = ClockDomain(reset_less=True)
        self.clock_domains.cd_pll4x  = ClockDomain(reset_less=True)
        self.clock_domains.cd_clk500 = ClockDomain()
32 33

        # # #
Piotr Binkowski's avatar
Piotr Binkowski committed
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

        self.submodules.pll = pll = USMMCM(speedgrade=-2)
        pll.register_clkin(platform.request("clk125"), 125e6)
        pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
        pll.create_clkout(self.cd_clk500, 500e6, with_reset=False)

        self.specials += [
            Instance("BUFGCE_DIV", name="main_bufgce_div",
                p_BUFGCE_DIVIDE=4,
                i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
            Instance("BUFGCE", name="main_bufgce",
                i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
            AsyncResetSynchronizer(self.cd_clk500, ~pll.locked),
        ]

49
        self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_clk500, cd_sys=self.cd_sys)
Piotr Binkowski's avatar
Piotr Binkowski committed
50 51 52

# BaseSoC ------------------------------------------------------------------------------------------

53
class BaseSoC(SoCCore):
Piotr Binkowski's avatar
Piotr Binkowski committed
54 55 56
    def __init__(self, sys_clk_freq=int(125e6), **kwargs):
        platform = zcu104.Platform()

57
        # SoCCore ----------------------------------------------------------------------------------
58
        SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
Piotr Binkowski's avatar
Piotr Binkowski committed
59 60 61 62 63 64

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # DDR4 SDRAM -------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
65
            self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
Piotr Binkowski's avatar
Piotr Binkowski committed
66
                memtype          = "DDR4",
67
                sys_clk_freq     = sys_clk_freq,
Piotr Binkowski's avatar
Piotr Binkowski committed
68
                iodelay_clk_freq = 500e6,
69
                cmd_latency      = 1)
Piotr Binkowski's avatar
Piotr Binkowski committed
70
            self.add_csr("ddrphy")
71 72
            self.add_sdram("sdram",
                phy                     = self.ddrphy,
73
                module                  = MTA4ATF51264HZ(sys_clk_freq, "1:4"),
74 75 76 77 78 79
                origin                  = self.mem_map["main_ram"],
                size                    = kwargs.get("max_sdram_size", 0x40000000),
                l2_cache_size           = kwargs.get("l2_size", 8192),
                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
                l2_cache_reverse        = True
            )
Piotr Binkowski's avatar
Piotr Binkowski committed
80

81
            self.submodules.i2c = I2CMaster(platform.request("i2c"))
Jędrzej Boczar's avatar
Jędrzej Boczar committed
82 83
            self.add_csr("i2c")

84 85 86 87 88 89
        # Leds -------------------------------------------------------------------------------------
        self.submodules.leds = LedChaser(
            pads         = Cat(*[platform.request("user_led", i) for i in range(4)]),
            sys_clk_freq = sys_clk_freq)
        self.add_csr("leds")

Piotr Binkowski's avatar
Piotr Binkowski committed
90 91 92 93
# Build --------------------------------------------------------------------------------------------

def main():
    parser = argparse.ArgumentParser(description="LiteX SoC on ZCU104")
94 95
    parser.add_argument("--build", action="store_true", help="Build bitstream")
    parser.add_argument("--load",  action="store_true", help="Load bitstream")
Piotr Binkowski's avatar
Piotr Binkowski committed
96 97 98 99 100 101
    builder_args(parser)
    soc_sdram_args(parser)
    args = parser.parse_args()

    soc = BaseSoC(**soc_sdram_argdict(args))
    builder = Builder(soc, **builder_argdict(args))
102
    builder.build(run=args.build)
Piotr Binkowski's avatar
Piotr Binkowski committed
103

104 105
    if args.load:
        prog = soc.platform.create_programmer()
106
        prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
Piotr Binkowski's avatar
Piotr Binkowski committed
107 108 109

if __name__ == "__main__":
    main()