This required inserting a wait state after every RAM read address update,
due to the data not reliably appearing on the read port until two clocks
after the address is set.  The iCE40 EBR blocks are poorly documented;
there is some evidence they act as if the output is registered even though
it is not officially stated as such.  Due to the lack of official documentation
combined with observed behavior, pipelining on the read ports was considered too
risky for the benefit gained.

This fixes the lack of inference and subsequent standard logic generation introducing
random skew between the derived RAM read clock and the original logic clock.

Tested to work with both get and set from Petitboot shell.
The POWER9 host also automatically loads the FPGA RTC time during startup.

This is cosmetic and does not change operation of the system in any way

Currently, only the power cap derate sensor is accessible

This completes the full HIOMAP interface

Fix incorrect window setup in main sequencer, especially
relating to write window start address

NOTE: The new HIOMAP erase command has not been tested as
the current version of hostboot does not make use of it.

The modified HDL was IPL checked to make sure no other
errors were introduced when this command was added to
the HIOMAP interface.

This is enough to allow OCC startup, IPL time now down to ~7 minutes

This resolves issues observed with spontaneous double IPMI response transmission
(i.e. same sequence ID and message contents) to host

This fixes sporadic outgoing (FPGA to host) IPMI message corruption

This fixes failure to re-IPL after host shutdown / restart

Signal new HIOMAP window creation with both read and write window types

Switch LPC firmware write cycles to write to internal cache RAM (if active) instead of external SPI Flash

This still needs FLUSH support to be functional

For now, use sector cache to back certain HIOMAP windows that fit within
the cache size available on the iCE40 (i.e., single sector windows).

The iCE40 only has ~12k of useable RAM once the other blocks are instantiated.
This isn't enough for us to cache and erase a full 64k block, but it is sufficient
to cache / erase a 4k subsector.  It is currently unknown if hostboot will demand
a write window of more than 12k -- if so, it will need modification to stay within
the 12k limit of the small FPGA device.

Basic (streamed) read working
IPL proceeds through ISTEP6,6 then halts at first write window creation attempt