This value is not provided in the specification, but appears to fall
well below actual TAR times as observed on IBM POWER9 hardware.

Extending to two clock cycles allows the bus to stabilize after
tristating has completed.

This was discovered and verified with physical IBM POWER9 hardware, as the
OpenFSI specification is silent on the format of the relative address offset.

Fix FSI slave parsing of REL_ADR address fields

This avoids potentially transmitting stale data on fast back to back reads

Adjust FSI master and slave core state machines to use more compact bitwise encoding
Add internal debug port to FSI master

This core implements the (relatively poorly documented) OpenFSI 1.0.0
specification available from the OpenPOWER Foundation.

As with the FSI master core, considerable uncertainty exists surrounding
error recovery and whether any extant FSI slaves honor error recovery
actions undertaken during I_POLL command processing, thus error recovery
is controlled by two independent enable bits in case incomaptible slaves
are enountered in the wild.

Invert FSI data in signal to match electrical interface specification

This core implements the (relatively poorly documented) OpenFSI 1.0.0
specification available from the OpenPOWER Foundation.

Considerable uncertainty exists surrounding error recovery and whether
any extant FSI slaves honor error recovery actions undertaken during
I_POLL command processing, thus error recovery is controlled by two
independent enable bits in case incomaptible slaves are enountered
in the wild.

This significantly speeds up system IPL, and represents the fastest
practical IPL speed for this small dual-PLL FPGA.

Larger FPGAs such as the quad PLL ECP5 should be able to reach the
100+MHz quad SPI maximum frequency when used with properly laid out
PCBs.

Switch main sequencer to use word transfer for firmware reads.

Use quad SPI I/O for all firmware read cycles.
This significantly improves overall IPL speed.

This avoids clock domain crossing glitches between the SPI
core and the sequencer logic.

Shave a master clock cycle off the SPI transfer by initiating frame start on transition from idle state

NVRAM should be considered mutable in the same way as the VPD
caches are considered mutable.  If NVRAM is to be locked, a different
define to lock out NVRAM should also be set.

This HDL dates from 2016-2017, and has not been tested on the same
hardware used for LPC slave development.

This does not alter operation of the generated system, it is a
cosmetic change only.

Mark completion in README file.

Ideally this would not be required in the first place, but hand-wired prototype
hardware still has a tendency to introduce a very small glitch or two in the reset
line over the long periods of time that the bridge needs to run with intensive data
transfer (firmware load).  These would normally be harmless if introduced on other
lines, but reset is both (for all intents and purposes) edge sensitive and a bit
of a sledgehammer to the system -- if it fires due to a glitch, the UART and LPC
bridge both drop and the UART won't come back without the host reconfiguring it...

The UART only needs to run at a bit under 2MHz.  Constrain the UART clock to
match this relaxed timing requirement.

This fixes an HDL grammar error found by iVerilog.  It does not change
functionality of the design in any way.

Remove the spurious input register disable option as it does not function and is not needed.

This avoids crossing clock domains and associated metastability
issues on the UART Wishbone interface.

This is no longer needed on the reworked prototype hardware

Tested to properly assert IRQ0/IRQ4 to a POWER9 host.