Shave a master clock cycle off the SPI transfer by initiating frame start on transition from idle state

NVRAM should be considered mutable in the same way as the VPD
caches are considered mutable.  If NVRAM is to be locked, a different
define to lock out NVRAM should also be set.

This HDL dates from 2016-2017, and has not been tested on the same
hardware used for LPC slave development.

This does not alter operation of the generated system, it is a
cosmetic change only.

Mark completion in README file.

Ideally this would not be required in the first place, but hand-wired prototype
hardware still has a tendency to introduce a very small glitch or two in the reset
line over the long periods of time that the bridge needs to run with intensive data
transfer (firmware load).  These would normally be harmless if introduced on other
lines, but reset is both (for all intents and purposes) edge sensitive and a bit
of a sledgehammer to the system -- if it fires due to a glitch, the UART and LPC
bridge both drop and the UART won't come back without the host reconfiguring it...

The UART only needs to run at a bit under 2MHz.  Constrain the UART clock to
match this relaxed timing requirement.

This fixes an HDL grammar error found by iVerilog.  It does not change
functionality of the design in any way.

Remove the spurious input register disable option as it does not function and is not needed.

This avoids crossing clock domains and associated metastability
issues on the UART Wishbone interface.

This is no longer needed on the reworked prototype hardware

Tested to properly assert IRQ0/IRQ4 to a POWER9 host.

This works around issues where the core would work if the state machine
registers were assigned to I/O pins, but fail otherwise.  It is likely
that setting them to zero prevents Yosys/NextPNR from randomly inserting
different initialization values and inverters that are not handled well
by the timing analysis.

See IPMI BT commit message for full details on the modifications required to
align the clocks while maintaining valid data transfer.

Also clean up extraneous conditions related to LPC address ready / address latching
in main sequencer.

See IPMI BT commit message for full details on the modifications required to
align the clocks while maintaining valid data transfer.

This required inserting a wait state after every RAM read address update,
due to the data not reliably appearing on the read port until two clocks
after the address is set.  The iCE40 EBR blocks are poorly documented;
there is some evidence they act as if the output is registered even though
it is not officially stated as such.  Due to the lack of official documentation
combined with observed behavior, pipelining on the read ports was considered too
risky for the benefit gained.

Wait for Wishbone cycle to complete before allowing LPC bus to finish write cycle

Earlier the phase differential between these two clocks was set
to zero.  Since random phase variations keep popping up between
these two clocks due to NextPNR's complete and utter lack of cross-
clock constraint support, officially lock them together at this
point.

This fixes the lack of inference and subsequent standard logic generation introducing
random skew between the derived RAM read clock and the original logic clock.

LPC clock timing issue is now resolved

Put sequencer clock on global clock buffer

Switch internal UART to be primary UART for hostboot / hvc0

This specifies the minimum operating frequency per-clock instead of
a global default, and improves reliability of the design across different
PAR runs (i.e when internal logic is modified).

Note that this does not (yet) replace the hostboot UART at 0x3f8,
it is to be used for development in parallel with hvc0 (COM1), and
was placed on COM2 (0x2f8) as a result.

Serial IRQ support plumbing still needs to be added.

This will be used to test IRQ handling over LPC

Tested to work with both get and set from Petitboot shell.
The POWER9 host also automatically loads the FPGA RTC time during startup.

OpenPOWER systems expect to be able to use the IPMI SEL get/set time commands to access the RTC via OPAL

Implementing the IPMI SEL and a basic RTC (active while FPGA has power / is configured) will avoid clock
reset / skew issues across host IPL cycles, provided the FPGA is not reset.

This does not interfere with IPL but does have the potential to throw
errors / warnings related to IPMI.  As implementation of FRU storage
is relatively simple, it should at least be an option for the bridge
device.

This is cosmetic and does not change operation of the system in any way

Currently, only the power cap derate sensor is accessible

This completes the full HIOMAP interface

Fix incorrect window setup in main sequencer, especially
relating to write window start address

NOTE: The new HIOMAP erase command has not been tested as
the current version of hostboot does not make use of it.

The modified HDL was IPL checked to make sure no other
errors were introduced when this command was added to
the HIOMAP interface.