Minor cleanup of default state handling in main sequencer

parent 30b4a5b9
...@@ -1640,6 +1640,10 @@ module lpc_bridge_top( ...@@ -1640,6 +1640,10 @@ module lpc_bridge_top(
cache_load_state <= BLOCK_CACHE_TRANSFER_STATE_IDLE; cache_load_state <= BLOCK_CACHE_TRANSFER_STATE_IDLE;
end end
end end
default: begin
// Should never reach this state
cache_load_state <= BLOCK_CACHE_INITIALIZE_STATE_01;
end
endcase endcase
case (fw_transfer_state) case (fw_transfer_state)
...@@ -2331,6 +2335,7 @@ module lpc_bridge_top( ...@@ -2331,6 +2335,7 @@ module lpc_bridge_top(
lpc_done_pulse_counter <= 0; lpc_done_pulse_counter <= 0;
end end
default: begin default: begin
// Should never reach this state
spi_external_master_cycle_start <= 0; spi_external_master_cycle_start <= 0;
fw_transfer_state <= LPC_BRIDGE_INITIALIZE_STATE_01; fw_transfer_state <= LPC_BRIDGE_INITIALIZE_STATE_01;
end end
......
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