diff --git a/fsi_master.v b/fsi_master.v
index d2f1da93c68784fd4e395aa9627e4669ed2fd2a5..57319482553dd121ec33bac7d7c7ca06b72a99cd 100644
--- a/fsi_master.v
+++ b/fsi_master.v
@@ -11,6 +11,7 @@ module fsi_master_interface(
 		input wire [1:0] data_length,			// 0 == 8 bit, 1 == 16 bit, 2 = 32 bit (NOTE: the lower two address bits may be forced if 16 bit / 32 bit transfer length is set)
 		input wire data_direction,			// 0 == read from slave, 1 == write to slave
 		input wire enable_relative_address,
+		input wire enable_crc_protection,
 		input wire start_cycle,
 		output wire cycle_complete,
 		output wire [2:0] cycle_error,
@@ -126,6 +127,7 @@ module fsi_master_interface(
 	reg [31:0] tx_data_reg = 0;
 	reg [31:0] rx_data_reg = 0;
 	reg enable_relative_address_reg = 0;
+	reg enable_crc_protection_reg = 0;
 	reg [1:0] enhanced_error_recovery_reg = 0;
 	reg [8:0] cycle_counter = 0;
 	reg [20:0] last_address = 0;
@@ -229,6 +231,7 @@ module fsi_master_interface(
 						endcase
 						tx_data_reg <= tx_data;
 						enable_relative_address_reg <= enable_relative_address;
+						enable_crc_protection_reg <= enable_crc_protection;
 						enhanced_error_recovery_reg <= enhanced_error_recovery;
 						slave_error_recovery_state <= 0;
 						master_error_recovery_state <= 0;
@@ -645,7 +648,7 @@ module fsi_master_interface(
 				end
 				FSI_TRANSFER_STATE_RX07: begin
 					crc_protected_bits_receiving = 0;
-					if (crc_data != 0) begin
+					if ((crc_data != 0) && enable_crc_protection_reg) begin
 						// Master received corrupted message from slave
 						if (((enhanced_error_recovery_reg[1] && ipoll_in_process)
 							|| (enhanced_error_recovery_reg[0] && !ipoll_in_process))
diff --git a/fsi_slave.v b/fsi_slave.v
index 7b064f493ee430dc1000343fcd8ebdcd8b8ec8f0..4f47a03b5545389ef2f94067b79c21970edde161 100644
--- a/fsi_slave.v
+++ b/fsi_slave.v
@@ -9,6 +9,7 @@ module fsi_slave_interface(
 		output wire [31:0] rx_data,
 		output wire [1:0] data_length,			// 0 == 8 bit, 1 == 16 bit, 2 = 32 bit
 		output wire data_direction,			// 0 == read from slave, 1 == write to slave
+		input wire enable_crc_protection,
 		output wire data_request_strobe,
 		input wire data_ready_strobe,
 		input wire [1:0] enhanced_error_recovery,	// Bit 1 == EER for IPOLL, Bit 0 == EER for all other transmissions
@@ -121,6 +122,7 @@ module fsi_slave_interface(
 	reg fsi_data_in_internal_prev = 0;
 	reg [20:0] address_rx_reg = 0;
 	reg [31:0] tx_data_reg = 0;
+	reg enable_crc_protection_reg = 0;
 	reg [1:0] enhanced_error_recovery_reg = 0;
 	reg [8:0] cycle_counter = 0;
 	reg [8:0] break_cycle_counter = 0;
@@ -184,6 +186,7 @@ module fsi_slave_interface(
 						// of a received BREAK command, it would result in continual
 						// error generation until the end of the command was received!
 						if (fsi_data_in_internal && !fsi_data_in_internal_prev) begin
+							enable_crc_protection_reg <= enable_crc_protection;
 							enhanced_error_recovery_reg <= enhanced_error_recovery;
 							crc_protected_bits_receiving = 1;
 							control_state <= FSI_TRANSFER_STATE_RX01;
@@ -433,7 +436,7 @@ module fsi_slave_interface(
 					end
 					FSI_TRANSFER_STATE_RX10: begin
 						crc_protected_bits_receiving = 0;
-						if (crc_data != 0) begin
+						if ((crc_data != 0) && enable_crc_protection_reg) begin
 							// Slave received corrupted message from master
 							if (((enhanced_error_recovery_reg[1] && ipoll_in_process)
 								|| (enhanced_error_recovery_reg[0] && !ipoll_in_process))